From 761e69df4e5b4dc60c68f8f2797e7fac8123d283 Mon Sep 17 00:00:00 2001
From: aprnath <aprnath@gmail.com>
Date: Wed, 4 Sep 2019 17:44:15 -0400
Subject: [PATCH] Update release-notes.md

---
 release-notes.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/release-notes.md b/release-notes.md
index f3e4255..3d8b0b7 100644
--- a/release-notes.md
+++ b/release-notes.md
@@ -1,7 +1,7 @@
 # SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital
 ## Release Notes
-1. Make the FPGA optimization code work with the latest version of Verilator.
-1. Move JTAG TAP to swerv_wrapper module.
+1. Make the FPGA optimization code work with the latest version of Verilator.[Pull request #13](https://github.com/chipsalliance/Cores-SweRV/pull/12)
+1. Move JTAG TAP to swerv_wrapper module. [Pull request #10](https://github.com/chipsalliance/Cores-SweRV/pull/10)
 
 # SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
 ## Release Notes