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Version 1.5

This commit is contained in:
Joseph Rahmeh 2020-02-19 18:24:28 -08:00
parent 36675abd25
commit 790c48cd0b
20 changed files with 5188 additions and 1484 deletions
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53
.gitignore vendored
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@ -1,7 +1,48 @@
configs/snapshots
work
obj_dir
*.vcd
*.csv
*.hex
# Exclude/Ignore file for git
*.log
RCS
*~
.*.swp
.*.swo
.DS_Store
*.[oa]
RCS/
snapshots/
.zenconfig
workspace/
workspace/work
# These are derived files
configs/common_defines.vh
configs/pd_defines.vh
configs/perl_configs.pl
configs/whisper.json
verif/diags/env/defines.h
design/include/pic_map_auto.h
design/include/pic_ctrl_verilator_unroll.sv
#codegenerators files
tools/codegenerators/AAPG/randomSeed.txt
tools/codegenerators/AAPG/aapg.pyc
tools/codegenerators/AAPG/baseInstructions.pyc
tools/codegenerators/AAPG/commonStuff.pyc
tools/codegenerators/AAPG/commonVar.pyc
tools/codegenerators/AAPG/config.pyc
tools/codegenerators/AAPG/opcodes.pyc
tools/codegenerators/AAPG/parseObjdump.pyc
tools/codegenerators/AAPG/result
tools/codegenerators/AAPG/standardExtensions.pyc
tools/codegenerators/csmith_run/platform.info
tools/codegenerators/csmith_run/syscalls.echx1
tools/codegenerators/csmith_run/syscalls.spike
tools/codegenerators/csmith_run/testdir_*
tools/codegenerators/riscv-torture/generator/target
tools/codegenerators/riscv-torture/project/target
tools/codegenerators/riscv-torture/testrun/target
verif/diags/C/csmith
verif/diags/reg
verif/vip/sdvt_ahb
tools/codegenerators/riscv-torture/output
tools/codegenerators/AAPG/randomSeed.txt
unit_level_testbench/pic/workspace/simulation/sim
tools/codegenerators/AAPGV2/swerv/asm/out*
tools/codegenerators/AAPGV2/swerv/bin/out*
tools/codegenerators/AAPGV2/swerv/objdump/out*

170
configs/snapshots/default/common_defines.vh
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by joseph.rahmeh on Tue Oct 15 13:13:16 PDT 2019
//
// cmd: swerv -snapshot=default -ahb_lite
//
`define RV_INST_ACCESS_MASK5 'hffffffff
`define RV_DATA_ACCESS_ENABLE4 1'h0
`define RV_INST_ACCESS_ENABLE3 1'h0
`define RV_INST_ACCESS_ENABLE0 1'h0
`define RV_INST_ACCESS_MASK3 'hffffffff
`define RV_DATA_ACCESS_ENABLE5 1'h0
`define RV_DATA_ACCESS_MASK5 'hffffffff
`define RV_DATA_ACCESS_ADDR3 'h00000000
`define RV_INST_ACCESS_ENABLE7 1'h0
`define RV_DATA_ACCESS_ADDR6 'h00000000
`define RV_INST_ACCESS_MASK7 'hffffffff
`define RV_INST_ACCESS_ENABLE6 1'h0
`define RV_INST_ACCESS_ENABLE5 1'h0
`define RV_DATA_ACCESS_ADDR4 'h00000000
`define RV_DATA_ACCESS_ADDR7 'h00000000
`define RV_DATA_ACCESS_MASK3 'hffffffff
`define RV_INST_ACCESS_MASK4 'hffffffff
`define RV_DATA_ACCESS_ADDR1 'h00000000
`define RV_INST_ACCESS_ADDR4 'h00000000
`define RV_INST_ACCESS_ADDR3 'h00000000
`define RV_DATA_ACCESS_ENABLE1 1'h0
`define RV_DATA_ACCESS_ADDR0 'h00000000
`define RV_DATA_ACCESS_MASK0 'hffffffff
`define RV_DATA_ACCESS_MASK6 'hffffffff
`define RV_INST_ACCESS_ADDR7 'h00000000
`define RV_INST_ACCESS_MASK0 'hffffffff
`define RV_DATA_ACCESS_ADDR5 'h00000000
`define RV_DATA_ACCESS_ADDR2 'h00000000
`define RV_DATA_ACCESS_MASK4 'hffffffff
`define RV_DATA_ACCESS_MASK1 'hffffffff
`define RV_INST_ACCESS_ADDR0 'h00000000
`define RV_INST_ACCESS_ADDR2 'h00000000
`define RV_DATA_ACCESS_ENABLE0 1'h0
`define RV_DATA_ACCESS_ENABLE2 1'h0
`define RV_DATA_ACCESS_ENABLE7 1'h0
`define RV_INST_ACCESS_ENABLE4 1'h0
`define RV_DATA_ACCESS_MASK7 'hffffffff
`define RV_INST_ACCESS_ADDR5 'h00000000
`define RV_INST_ACCESS_ENABLE1 1'h0
`define RV_DATA_ACCESS_MASK2 'hffffffff
`define RV_INST_ACCESS_MASK6 'hffffffff
`define RV_DATA_ACCESS_ENABLE3 1'h0
`define RV_INST_ACCESS_ADDR6 'h00000000
`define RV_INST_ACCESS_MASK2 'hffffffff
`define RV_INST_ACCESS_ENABLE2 1'h0
`define RV_DATA_ACCESS_ENABLE6 1'h0
`define RV_INST_ACCESS_ADDR1 'h00000000
`define RV_INST_ACCESS_MASK1 'hffffffff
`define RV_DEC_INSTBUF_DEPTH 4
`define RV_DMA_BUF_DEPTH 4
`define RV_LSU_NUM_NBLOAD 8
`define RV_LSU_STBUF_DEPTH 8
`define RV_LSU_NUM_NBLOAD_WIDTH 3
`define RV_IFU_BUS_TAG 3
`define RV_LSU_BUS_TAG 4
`define RV_SB_BUS_TAG 1
`define RV_DMA_BUS_TAG 1
`define RV_DCCM_WIDTH_BITS 2
`define RV_DCCM_REGION 4'hf
`define RV_DCCM_RESERVED 'h1000
`define RV_DCCM_SIZE 64
`define RV_DCCM_DATA_WIDTH 32
`define RV_DCCM_NUM_BANKS_8
`define RV_DCCM_FDATA_WIDTH 39
`define RV_DCCM_BYTE_WIDTH 4
`define RV_DCCM_DATA_CELL ram_2048x39
`define RV_DCCM_ENABLE 1
`define RV_DCCM_BITS 16
`define RV_DCCM_OFFSET 28'h40000
`define RV_DCCM_ECC_WIDTH 7
`define RV_DCCM_SIZE_64
`define RV_DCCM_ROWS 2048
`define RV_DCCM_BANK_BITS 3
`define RV_DCCM_NUM_BANKS 8
`define RV_DCCM_INDEX_BITS 11
`define RV_LSU_SB_BITS 16
`define RV_DCCM_EADR 32'hf004ffff
`define RV_DCCM_SADR 32'hf0040000
`define RV_RESET_VEC 'h80000000
`define RV_RET_STACK_SIZE 4
`define RV_XLEN 32
`define RV_TARGET default
`define RV_BTB_BTAG_FOLD 1
`define RV_BTB_INDEX3_HI 9
`define RV_BTB_INDEX1_LO 4
`define RV_BTB_ADDR_HI 5
`define RV_BTB_ADDR_LO 4
`define RV_BTB_INDEX1_HI 5
`define RV_BTB_INDEX2_HI 7
`define RV_BTB_INDEX2_LO 6
`define RV_BTB_ARRAY_DEPTH 4
`define RV_BTB_BTAG_SIZE 9
`define RV_BTB_SIZE 32
`define RV_BTB_INDEX3_LO 8
`define RV_ICCM_NUM_BANKS 8
`define RV_ICCM_BITS 19
`define RV_ICCM_BANK_BITS 3
`define RV_ICCM_ROWS 16384
`define RV_ICCM_OFFSET 10'he000000
`define RV_ICCM_REGION 4'he
`define RV_ICCM_SADR 32'hee000000
`define RV_ICCM_RESERVED 'h1000
`define RV_ICCM_DATA_CELL ram_16384x39
`define RV_ICCM_INDEX_BITS 14
`define RV_ICCM_NUM_BANKS_8
`define RV_ICCM_SIZE 512
`define RV_ICCM_EADR 32'hee07ffff
`define RV_ICCM_SIZE_512
`define RV_ICACHE_SIZE 16
`define RV_ICACHE_TAG_HIGH 12
`define RV_ICACHE_IC_ROWS 256
`define RV_ICACHE_TADDR_HIGH 5
`define RV_ICACHE_TAG_LOW 6
`define RV_ICACHE_TAG_CELL ram_64x21
`define RV_ICACHE_IC_DEPTH 8
`define RV_ICACHE_IC_INDEX 8
`define RV_ICACHE_ENABLE 1
`define RV_ICACHE_DATA_CELL ram_256x34
`define RV_ICACHE_TAG_DEPTH 64
`define RV_EXTERNAL_PROG 'hb0000000
`define RV_EXTERNAL_DATA_1 'h00000000
`define RV_DEBUG_SB_MEM 'hb0580000
`define RV_EXTERNAL_DATA 'hc0580000
`define RV_SERIALIO 'hd0580000
`define RV_NMI_VEC 'h11110000
`define RV_BHT_HASH_STRING {ghr[3:2] ^ {ghr[3+1], {4-1-2{1'b0} } },hashin[5:4]^ghr[2-1:0]}
`define RV_BHT_ADDR_HI 7
`define RV_BHT_GHR_RANGE 4:0
`define RV_BHT_GHR_SIZE 5
`define RV_BHT_GHR_PAD2 fghr[4:3],2'b0
`define RV_BHT_SIZE 128
`define RV_BHT_ADDR_LO 4
`define RV_BHT_ARRAY_DEPTH 16
`define RV_BHT_GHR_PAD fghr[4],3'b0
`define RV_NUMIREGS 32
`define RV_PIC_BITS 15
`define RV_PIC_REGION 4'hf
`define RV_PIC_INT_WORDS 1
`define RV_PIC_TOTAL_INT_PLUS1 9
`define RV_PIC_MEIP_OFFSET 'h1000
`define RV_PIC_BASE_ADDR 32'hf00c0000
`define RV_PIC_MEIGWCTRL_OFFSET 'h4000
`define RV_PIC_MEIPL_OFFSET 'h0000
`define RV_PIC_TOTAL_INT 8
`define RV_PIC_SIZE 32
`define RV_PIC_MEIE_OFFSET 'h2000
`define RV_PIC_OFFSET 10'hc0000
`define RV_PIC_MEIPT_OFFSET 'h3004
`define RV_PIC_MPICCFG_OFFSET 'h3000
`define RV_PIC_MEIGWCLR_OFFSET 'h5000
`define CLOCK_PERIOD 100
`define CPU_TOP `RV_TOP.swerv
`define TOP tb_top
`define RV_BUILD_AHB_LITE 1
`define RV_TOP `TOP.rvtop
`define DATAWIDTH 64
`define RV_STERR_ROLLBACK 0
`define RV_EXT_ADDRWIDTH 32
`define RV_EXT_DATAWIDTH 64
`define SDVT_AHB 1
`define RV_LDERR_ROLLBACK 1
`define ASSERT_ON
`define TEC_RV_ICG clockhdr
`define REGWIDTH 32
`undef ASSERT_ON

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configs/snapshots/default/defines.h
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by joseph.rahmeh on Tue Oct 15 13:13:16 PDT 2019
//
// cmd: swerv -snapshot=default -ahb_lite
//
#define RV_INST_ACCESS_MASK5 0xffffffff
#define RV_DATA_ACCESS_ENABLE4 0x0
#define RV_INST_ACCESS_ENABLE3 0x0
#define RV_INST_ACCESS_ENABLE0 0x0
#define RV_INST_ACCESS_MASK3 0xffffffff
#define RV_DATA_ACCESS_ENABLE5 0x0
#define RV_DATA_ACCESS_MASK5 0xffffffff
#define RV_DATA_ACCESS_ADDR3 0x00000000
#define RV_INST_ACCESS_ENABLE7 0x0
#define RV_DATA_ACCESS_ADDR6 0x00000000
#define RV_INST_ACCESS_MASK7 0xffffffff
#define RV_INST_ACCESS_ENABLE6 0x0
#define RV_INST_ACCESS_ENABLE5 0x0
#define RV_DATA_ACCESS_ADDR4 0x00000000
#define RV_DATA_ACCESS_ADDR7 0x00000000
#define RV_DATA_ACCESS_MASK3 0xffffffff
#define RV_INST_ACCESS_MASK4 0xffffffff
#define RV_DATA_ACCESS_ADDR1 0x00000000
#define RV_INST_ACCESS_ADDR4 0x00000000
#define RV_INST_ACCESS_ADDR3 0x00000000
#define RV_DATA_ACCESS_ENABLE1 0x0
#define RV_DATA_ACCESS_ADDR0 0x00000000
#define RV_DATA_ACCESS_MASK0 0xffffffff
#define RV_DATA_ACCESS_MASK6 0xffffffff
#define RV_INST_ACCESS_ADDR7 0x00000000
#define RV_INST_ACCESS_MASK0 0xffffffff
#define RV_DATA_ACCESS_ADDR5 0x00000000
#define RV_DATA_ACCESS_ADDR2 0x00000000
#define RV_DATA_ACCESS_MASK4 0xffffffff
#define RV_DATA_ACCESS_MASK1 0xffffffff
#define RV_INST_ACCESS_ADDR0 0x00000000
#define RV_INST_ACCESS_ADDR2 0x00000000
#define RV_DATA_ACCESS_ENABLE0 0x0
#define RV_DATA_ACCESS_ENABLE2 0x0
#define RV_DATA_ACCESS_ENABLE7 0x0
#define RV_INST_ACCESS_ENABLE4 0x0
#define RV_DATA_ACCESS_MASK7 0xffffffff
#define RV_INST_ACCESS_ADDR5 0x00000000
#define RV_INST_ACCESS_ENABLE1 0x0
#define RV_DATA_ACCESS_MASK2 0xffffffff
#define RV_INST_ACCESS_MASK6 0xffffffff
#define RV_DATA_ACCESS_ENABLE3 0x0
#define RV_INST_ACCESS_ADDR6 0x00000000
#define RV_INST_ACCESS_MASK2 0xffffffff
#define RV_INST_ACCESS_ENABLE2 0x0
#define RV_DATA_ACCESS_ENABLE6 0x0
#define RV_INST_ACCESS_ADDR1 0x00000000
#define RV_INST_ACCESS_MASK1 0xffffffff
#define RV_IFU_BUS_TAG 3
#define RV_LSU_BUS_TAG 4
#define RV_SB_BUS_TAG 1
#define RV_DMA_BUS_TAG 1
#define RV_DCCM_WIDTH_BITS 2
#define RV_DCCM_REGION 0xf
#define RV_DCCM_RESERVED 0x1000
#define RV_DCCM_SIZE 64
#define RV_DCCM_DATA_WIDTH 32
#define RV_DCCM_NUM_BANKS_8
#define RV_DCCM_FDATA_WIDTH 39
#define RV_DCCM_BYTE_WIDTH 4
#define RV_DCCM_DATA_CELL ram_2048x39
#define RV_DCCM_ENABLE 1
#define RV_DCCM_BITS 16
#define RV_DCCM_OFFSET 0x40000
#define RV_DCCM_ECC_WIDTH 7
#define RV_DCCM_SIZE_64
#define RV_DCCM_ROWS 2048
#define RV_DCCM_BANK_BITS 3
#define RV_DCCM_NUM_BANKS 8
#define RV_DCCM_INDEX_BITS 11
#define RV_LSU_SB_BITS 16
#define RV_DCCM_EADR 0xf004ffff
#define RV_DCCM_SADR 0xf0040000
#ifndef RV_RESET_VEC
#define RV_RESET_VEC 0x80000000
#endif
#define RV_XLEN 32
#define RV_TARGET default
#define RV_ICCM_NUM_BANKS 8
#define RV_ICCM_BITS 19
#define RV_ICCM_BANK_BITS 3
#define RV_ICCM_ROWS 16384
#define RV_ICCM_OFFSET 0xe000000
#define RV_ICCM_REGION 0xe
#define RV_ICCM_SADR 0xee000000
#define RV_ICCM_RESERVED 0x1000
#define RV_ICCM_DATA_CELL ram_16384x39
#define RV_ICCM_INDEX_BITS 14
#define RV_ICCM_NUM_BANKS_8
#define RV_ICCM_SIZE 512
#define RV_ICCM_EADR 0xee07ffff
#define RV_ICCM_SIZE_512
#define RV_EXTERNAL_PROG 0xb0000000
#define RV_EXTERNAL_DATA_1 0x00000000
#define RV_DEBUG_SB_MEM 0xb0580000
#define RV_EXTERNAL_DATA 0xc0580000
#define RV_SERIALIO 0xd0580000
#ifndef RV_NMI_VEC
#define RV_NMI_VEC 0x11110000
#endif
#define RV_PIC_BITS 15
#define RV_PIC_REGION 0xf
#define RV_PIC_INT_WORDS 1
#define RV_PIC_TOTAL_INT_PLUS1 9
#define RV_PIC_MEIP_OFFSET 0x1000
#define RV_PIC_BASE_ADDR 0xf00c0000
#define RV_PIC_MEIGWCTRL_OFFSET 0x4000
#define RV_PIC_MEIPL_OFFSET 0x0000
#define RV_PIC_TOTAL_INT 8
#define RV_PIC_SIZE 32
#define RV_PIC_MEIE_OFFSET 0x2000
#define RV_PIC_OFFSET 0xc0000
#define RV_PIC_MEIPT_OFFSET 0x3004
#define RV_PIC_MPICCFG_OFFSET 0x3000
#define RV_PIC_MEIGWCLR_OFFSET 0x5000
#define CLOCK_PERIOD 100
#define CPU_TOP `RV_TOP.swerv
#define TOP tb_top
#define RV_BUILD_AHB_LITE 1
#define RV_TOP `TOP.rvtop
#define DATAWIDTH 64
#define RV_STERR_ROLLBACK 0
#define RV_EXT_ADDRWIDTH 32
#define RV_EXT_DATAWIDTH 64
#define SDVT_AHB 1
#define RV_LDERR_ROLLBACK 1
#define ASSERT_ON

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configs/snapshots/default/pd_defines.vh
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by joseph.rahmeh on Tue Oct 15 13:13:16 PDT 2019
//
// cmd: swerv -snapshot=default -ahb_lite
//
`include "common_defines.vh"
`undef ASSERT_ON
`undef TEC_RV_ICG
`define TEC_RV_ICG CKLNQD12BWP35P140
`define PHYSICAL 1

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configs/snapshots/default/perl_configs.pl
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# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
# This is an automatically generated file by joseph.rahmeh on Tue Oct 15 13:13:16 PDT 2019
#
# cmd: swerv -snapshot=default -ahb_lite
#
# To use this in a perf script, use 'require $RV_ROOT/configs/config.pl'
# Reference the hash via $config{name}..
%config = (
'protection' => {
'inst_access_mask5' => '0xffffffff',
'data_access_enable4' => '0x0',
'inst_access_enable3' => '0x0',
'inst_access_enable0' => '0x0',
'inst_access_mask3' => '0xffffffff',
'data_access_enable5' => '0x0',
'data_access_mask5' => '0xffffffff',
'data_access_addr3' => '0x00000000',
'inst_access_enable7' => '0x0',
'data_access_addr6' => '0x00000000',
'inst_access_mask7' => '0xffffffff',
'inst_access_enable6' => '0x0',
'inst_access_enable5' => '0x0',
'data_access_addr4' => '0x00000000',
'data_access_addr7' => '0x00000000',
'data_access_mask3' => '0xffffffff',
'inst_access_mask4' => '0xffffffff',
'data_access_addr1' => '0x00000000',
'inst_access_addr4' => '0x00000000',
'inst_access_addr3' => '0x00000000',
'data_access_enable1' => '0x0',
'data_access_addr0' => '0x00000000',
'data_access_mask0' => '0xffffffff',
'data_access_mask6' => '0xffffffff',
'inst_access_addr7' => '0x00000000',
'inst_access_mask0' => '0xffffffff',
'data_access_addr5' => '0x00000000',
'data_access_addr2' => '0x00000000',
'data_access_mask4' => '0xffffffff',
'data_access_mask1' => '0xffffffff',
'inst_access_addr0' => '0x00000000',
'inst_access_addr2' => '0x00000000',
'data_access_enable0' => '0x0',
'data_access_enable2' => '0x0',
'data_access_enable7' => '0x0',
'inst_access_enable4' => '0x0',
'data_access_mask7' => '0xffffffff',
'inst_access_addr5' => '0x00000000',
'inst_access_enable1' => '0x0',
'data_access_mask2' => '0xffffffff',
'inst_access_mask6' => '0xffffffff',
'data_access_enable3' => '0x0',
'inst_access_addr6' => '0x00000000',
'inst_access_mask2' => '0xffffffff',
'inst_access_enable2' => '0x0',
'data_access_enable6' => '0x0',
'inst_access_addr1' => '0x00000000',
'inst_access_mask1' => '0xffffffff'
},
'core' => {
'dec_instbuf_depth' => '4',
'dma_buf_depth' => '4',
'lsu_num_nbload' => '8',
'lsu_stbuf_depth' => '8',
'lsu_num_nbload_width' => '3'
},
'bus' => {
'ifu_bus_tag' => '3',
'lsu_bus_tag' => 4,
'sb_bus_tag' => '1',
'dma_bus_tag' => '1'
},
'dccm' => {
'dccm_width_bits' => 2,
'dccm_region' => '0xf',
'dccm_reserved' => '0x1000',
'dccm_size' => 64,
'dccm_data_width' => 32,
'dccm_num_banks_8' => '',
'dccm_fdata_width' => 39,
'dccm_byte_width' => '4',
'dccm_data_cell' => 'ram_2048x39',
'dccm_enable' => '1',
'dccm_bits' => 16,
'dccm_offset' => '0x40000',
'dccm_ecc_width' => 7,
'dccm_size_64' => '',
'dccm_rows' => '2048',
'dccm_bank_bits' => 3,
'dccm_num_banks' => '8',
'dccm_index_bits' => 11,
'lsu_sb_bits' => 16,
'dccm_eadr' => '0xf004ffff',
'dccm_sadr' => '0xf0040000'
},
'reset_vec' => '0x80000000',
'retstack' => {
'ret_stack_size' => '4'
},
'triggers' => [
{
'poke_mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
],
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
],
'mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
]
},
{
'poke_mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
],
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
],
'mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
]
},
{
'poke_mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
],
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
],
'mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
]
},
{
'poke_mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
],
'reset' => [
'0x23e00000',
'0x00000000',
'0x00000000'
],
'mask' => [
'0x081818c7',
'0xffffffff',
'0x00000000'
]
}
],
'xlen' => 32,
'verilator' => '',
'target' => 'default',
'max_mmode_perf_event' => '50',
'btb' => {
'btb_btag_fold' => 1,
'btb_index3_hi' => 9,
'btb_index1_lo' => '4',
'btb_addr_hi' => 5,
'btb_addr_lo' => '4',
'btb_index1_hi' => 5,
'btb_index2_hi' => 7,
'btb_index2_lo' => 6,
'btb_array_depth' => 4,
'btb_btag_size' => 9,
'btb_size' => 32,
'btb_index3_lo' => 8
},
'iccm' => {
'iccm_num_banks' => '8',
'iccm_bits' => 19,
'iccm_bank_bits' => 3,
'iccm_rows' => '16384',
'iccm_offset' => '0xe000000',
'iccm_region' => '0xe',
'iccm_sadr' => '0xee000000',
'iccm_reserved' => '0x1000',
'iccm_data_cell' => 'ram_16384x39',
'iccm_index_bits' => 14,
'iccm_num_banks_8' => '',
'iccm_size' => 512,
'iccm_eadr' => '0xee07ffff',
'iccm_size_512' => ''
},
'icache' => {
'icache_size' => 16,
'icache_tag_high' => 12,
'icache_ic_rows' => '256',
'icache_taddr_high' => 5,
'icache_tag_low' => '6',
'icache_tag_cell' => 'ram_64x21',
'icache_ic_depth' => 8,
'icache_ic_index' => 8,
'icache_enable' => '1',
'icache_data_cell' => 'ram_256x34',
'icache_tag_depth' => 64
},
'physical' => '1',
'memmap' => {
'external_prog' => '0xb0000000',
'external_data_1' => '0x00000000',
'debug_sb_mem' => '0xb0580000',
'external_data' => '0xc0580000',
'serialio' => '0xd0580000'
},
'nmi_vec' => '0x11110000',
'num_mmode_perf_regs' => '4',
'bht' => {
'bht_hash_string' => '{ghr[3:2] ^ {ghr[3+1], {4-1-2{1\'b0} } },hashin[5:4]^ghr[2-1:0]}',
'bht_addr_hi' => 7,
'bht_ghr_range' => '4:0',
'bht_ghr_size' => 5,
'bht_ghr_pad2' => 'fghr[4:3],2\'b0',
'bht_size' => 128,
'bht_addr_lo' => '4',
'bht_array_depth' => 16,
'bht_ghr_pad' => 'fghr[4],3\'b0'
},
'numiregs' => '32',
'even_odd_trigger_chains' => 'true',
'pic' => {
'pic_bits' => 15,
'pic_region' => '0xf',
'pic_int_words' => 1,
'pic_total_int_plus1' => 9,
'pic_meip_offset' => '0x1000',
'pic_base_addr' => '0xf00c0000',
'pic_meigwctrl_offset' => '0x4000',
'pic_meipl_offset' => '0x0000',
'pic_total_int' => 8,
'pic_size' => 32,
'pic_meie_offset' => '0x2000',
'pic_offset' => '0xc0000',
'pic_meipt_offset' => '0x3004',
'pic_mpiccfg_offset' => '0x3000',
'pic_meigwclr_offset' => '0x5000'
},
'testbench' => {
'clock_period' => '100',
'CPU_TOP' => '`RV_TOP.swerv',
'TOP' => 'tb_top',
'build_ahb_lite' => '1',
'RV_TOP' => '`TOP.rvtop',
'datawidth' => '64',
'sterr_rollback' => '0',
'ext_addrwidth' => '32',
'ext_datawidth' => '64',
'SDVT_AHB' => '1',
'lderr_rollback' => '1',
'assert_on' => ''
},
'tec_rv_icg' => 'clockhdr',
'csr' => {
'pmpaddr9' => {
'exists' => 'false'
},
'dicad1' => {
'reset' => '0x0',
'number' => '0x7ca',
'comment' => 'Cache diagnostics.',
'debug' => 'true',
'exists' => 'true',
'mask' => '0x3'
},
'pmpcfg0' => {
'exists' => 'false'
},
'mhpmcounter4h' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'dicago' => {
'reset' => '0x0',
'number' => '0x7cb',
'comment' => 'Cache diagnostics.',
'debug' => 'true',
'exists' => 'true',
'mask' => '0x0'
},
'mie' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0x40000888'
},
'misa' => {
'reset' => '0x40001104',
'exists' => 'true',
'mask' => '0x0'
},
'mhpmcounter6h' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'meicpct' => {
'reset' => '0x0',
'number' => '0xbca',
'comment' => 'External claim id/priority capture.',
'exists' => 'true',
'mask' => '0x0'
},
'mimpid' => {
'reset' => '0x1',
'exists' => 'true',
'mask' => '0x0'
},
'mcpc' => {
'reset' => '0x0',
'number' => '0x7c2',
'exists' => 'true',
'mask' => '0x0'
},
'mhpmevent4' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'pmpaddr8' => {
'exists' => 'false'
},
'pmpcfg3' => {
'exists' => 'false'
},
'marchid' => {
'reset' => '0x0000000b',
'exists' => 'true',
'mask' => '0x0'
},
'pmpaddr5' => {
'exists' => 'false'
},
'mfdc' => {
'reset' => '0x00070000',
'number' => '0x7f9',
'exists' => 'true',
'mask' => '0x000707ff'
},
'mhpmevent6' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'mvendorid' => {
'reset' => '0x45',
'exists' => 'true',
'mask' => '0x0'
},
'pmpaddr4' => {
'exists' => 'false'
},
'dcsr' => {
'poke_mask' => '0x00008dcc',
'reset' => '0x40000003',
'exists' => 'true',
'mask' => '0x00008c04'
},
'cycle' => {
'exists' => 'false'
},
'pmpaddr12' => {
'exists' => 'false'
},
'pmpaddr3' => {
'exists' => 'false'
},
'mhpmcounter3h' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'time' => {
'exists' => 'false'
},
'meicidpl' => {
'reset' => '0x0',
'number' => '0xbcb',
'comment' => 'External interrupt claim id priority level.',
'exists' => 'true',
'mask' => '0xf'
},
'pmpaddr14' => {
'exists' => 'false'
},
'pmpaddr13' => {
'exists' => 'false'
},
'pmpaddr1' => {
'exists' => 'false'
},
'mhpmcounter6' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'dicad0' => {
'reset' => '0x0',
'number' => '0x7c9',
'comment' => 'Cache diagnostics.',
'debug' => 'true',
'exists' => 'true',
'mask' => '0xffffffff'
},
'meipt' => {
'reset' => '0x0',
'number' => '0xbc9',
'comment' => 'External interrupt priority threshold.',
'exists' => 'true',
'mask' => '0xf'
},
'pmpaddr15' => {
'exists' => 'false'
},
'mhpmcounter5' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'pmpcfg1' => {
'exists' => 'false'
},
'pmpaddr10' => {
'exists' => 'false'
},
'pmpaddr0' => {
'exists' => 'false'
},
'pmpcfg2' => {
'exists' => 'false'
},
'pmpaddr2' => {
'exists' => 'false'
},
'mpmc' => {
'reset' => '0x0',
'number' => '0x7c6',
'comment' => 'Core pause: Implemented as read only.',
'exists' => 'true',
'mask' => '0x0'
},
'dmst' => {
'reset' => '0x0',
'number' => '0x7c4',
'comment' => 'Memory synch trigger: Flush caches in debug mode.',
'debug' => 'true',
'exists' => 'true',
'mask' => '0x0'
},
'instret' => {
'exists' => 'false'
},
'mhpmevent3' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'dicawics' => {
'reset' => '0x0',
'number' => '0x7c8',
'comment' => 'Cache diagnostics.',
'debug' => 'true',
'exists' => 'true',
'mask' => '0x0130fffc'
},
'mip' => {
'poke_mask' => '0x40000888',
'reset' => '0x0',
'exists' => 'true',
'mask' => '0x0'
},
'mhpmcounter5h' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'micect' => {
'reset' => '0x0',
'number' => '0x7f0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'miccmect' => {
'reset' => '0x0',
'number' => '0x7f1',
'exists' => 'true',
'mask' => '0xffffffff'
},
'mhpmevent5' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'mhpmcounter3' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'pmpaddr6' => {
'exists' => 'false'
},
'pmpaddr11' => {
'exists' => 'false'
},
'mcgc' => {
'poke_mask' => '0x000001ff',
'reset' => '0x0',
'number' => '0x7f8',
'exists' => 'true',
'mask' => '0x000001ff'
},
'mhpmcounter4' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0xffffffff'
},
'mdccmect' => {
'reset' => '0x0',
'number' => '0x7f2',
'exists' => 'true',
'mask' => '0xffffffff'
},
'pmpaddr7' => {
'exists' => 'false'
},
'meicurpl' => {
'reset' => '0x0',
'number' => '0xbcc',
'comment' => 'External interrupt current priority level.',
'exists' => 'true',
'mask' => '0xf'
},
'mstatus' => {
'reset' => '0x1800',
'exists' => 'true',
'mask' => '0x88'
},
'tselect' => {
'reset' => '0x0',
'exists' => 'true',
'mask' => '0x3'
}
},
'regwidth' => '32',
'harts' => 1
);
1;

173
configs/snapshots/default/pic_ctrl_verilator_unroll.sv
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@ -1,173 +0,0 @@
// argv=9
// TOTAL_INT=9 NUM_LEVELS=4
`ifdef RV_PIC_2CYCLE
// LEVEL0
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_1;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_1;
for (m=0; m<=(TOTAL_INT)/(2**(1)) ; m++) begin : COMPARE0
if ( m == (TOTAL_INT)/(2**(1))) begin
assign level_intpend_w_prior_en_1[m+1] = '0 ;
assign level_intpend_id_1[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
.a_id(level_intpend_id[0][2*m]),
.a_priority(level_intpend_w_prior_en[0][2*m]),
.b_id(level_intpend_id[0][2*m+1]),
.b_priority(level_intpend_w_prior_en[0][2*m+1]),
.out_id(level_intpend_id_1[m]),
.out_priority(level_intpend_w_prior_en_1[m])) ;
end
// LEVEL1
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_2;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_2;
for (m=0; m<=(TOTAL_INT)/(2**(2)) ; m++) begin : COMPARE1
if ( m == (TOTAL_INT)/(2**(2))) begin
assign level_intpend_w_prior_en_2[m+1] = '0 ;
assign level_intpend_id_2[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l2 (
.a_id(level_intpend_id_1[2*m]),
.a_priority(level_intpend_w_prior_en_1[2*m]),
.b_id(level_intpend_id_1[2*m+1]),
.b_priority(level_intpend_w_prior_en_1[2*m+1]),
.out_id(level_intpend_id_2[m]),
.out_priority(level_intpend_w_prior_en_2[m])) ;
end
for (i=0; i<=TOTAL_INT/2**(NUM_LEVELS/2) ; i++) begin : MIDDLE_FLOPS
rvdff #(INTPRIORITY_BITS) level2_intpend_prior_reg (.*, .din (level_intpend_w_prior_en_2[i]), .dout(l2_intpend_w_prior_en_ff[i]), .clk(active_clk));
rvdff #(ID_BITS) level2_intpend_id_reg (.*, .din (level_intpend_id_2[i]), .dout(l2_intpend_id_ff[i]), .clk(active_clk));
end
// LEVEL2
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] levelx_intpend_w_prior_en_3;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] levelx_intpend_id_3;
for (m=0; m<=(TOTAL_INT)/(2**(3)) ; m++) begin : COMPARE2
if ( m == (TOTAL_INT)/(2**(3))) begin
assign levelx_intpend_w_prior_en_3[m+1] = '0 ;
assign levelx_intpend_id_3[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l3 (
.a_id(levelx_intpend_id[2][2*m]),
.a_priority(levelx_intpend_w_prior_en[2][2*m]),
.b_id(levelx_intpend_id[2][2*m+1]),
.b_priority(levelx_intpend_w_prior_en[2][2*m+1]),
.out_id(levelx_intpend_id_3[m]),
.out_priority(levelx_intpend_w_prior_en_3[m])) ;
end
// LEVEL3
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] levelx_intpend_w_prior_en_4;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] levelx_intpend_id_4;
for (m=0; m<=(TOTAL_INT)/(2**(4)) ; m++) begin : COMPARE3
if ( m == (TOTAL_INT)/(2**(4))) begin
assign levelx_intpend_w_prior_en_4[m+1] = '0 ;
assign levelx_intpend_id_4[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l4 (
.a_id(levelx_intpend_id_3[2*m]),
.a_priority(levelx_intpend_w_prior_en_3[2*m]),
.b_id(levelx_intpend_id_3[2*m+1]),
.b_priority(levelx_intpend_w_prior_en_3[2*m+1]),
.out_id(levelx_intpend_id_4[m]),
.out_priority(levelx_intpend_w_prior_en_4[m])) ;
end
assign claimid_in[ID_BITS-1:0] = levelx_intpend_id_4[0] ; // This is the last level output
assign selected_int_priority[INTPRIORITY_BITS-1:0] = levelx_intpend_w_prior_en_4[0] ;
`else
// LEVEL0
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_1;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_1;
for (m=0; m<=(TOTAL_INT)/(2**(1)) ; m++) begin : COMPARE0
if ( m == (TOTAL_INT)/(2**(1))) begin
assign level_intpend_w_prior_en_1[m+1] = '0 ;
assign level_intpend_id_1[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 (
.a_id(level_intpend_id[0][2*m]),
.a_priority(level_intpend_w_prior_en[0][2*m]),
.b_id(level_intpend_id[0][2*m+1]),
.b_priority(level_intpend_w_prior_en[0][2*m+1]),
.out_id(level_intpend_id_1[m]),
.out_priority(level_intpend_w_prior_en_1[m])) ;
end
// LEVEL1
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_2;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_2;
for (m=0; m<=(TOTAL_INT)/(2**(2)) ; m++) begin : COMPARE1
if ( m == (TOTAL_INT)/(2**(2))) begin
assign level_intpend_w_prior_en_2[m+1] = '0 ;
assign level_intpend_id_2[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l2 (
.a_id(level_intpend_id_1[2*m]),
.a_priority(level_intpend_w_prior_en_1[2*m]),
.b_id(level_intpend_id_1[2*m+1]),
.b_priority(level_intpend_w_prior_en_1[2*m+1]),
.out_id(level_intpend_id_2[m]),
.out_priority(level_intpend_w_prior_en_2[m])) ;
end
// LEVEL2
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_3;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_3;
for (m=0; m<=(TOTAL_INT)/(2**(3)) ; m++) begin : COMPARE2
if ( m == (TOTAL_INT)/(2**(3))) begin
assign level_intpend_w_prior_en_3[m+1] = '0 ;
assign level_intpend_id_3[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l3 (
.a_id(level_intpend_id_2[2*m]),
.a_priority(level_intpend_w_prior_en_2[2*m]),
.b_id(level_intpend_id_2[2*m+1]),
.b_priority(level_intpend_w_prior_en_2[2*m+1]),
.out_id(level_intpend_id_3[m]),
.out_priority(level_intpend_w_prior_en_3[m])) ;
end
// LEVEL3
logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_4;
logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_4;
for (m=0; m<=(TOTAL_INT)/(2**(4)) ; m++) begin : COMPARE3
if ( m == (TOTAL_INT)/(2**(4))) begin
assign level_intpend_w_prior_en_4[m+1] = '0 ;
assign level_intpend_id_4[m+1] = '0 ;
end
cmp_and_mux #(
.ID_BITS(ID_BITS),
.INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l4 (
.a_id(level_intpend_id_3[2*m]),
.a_priority(level_intpend_w_prior_en_3[2*m]),
.b_id(level_intpend_id_3[2*m+1]),
.b_priority(level_intpend_w_prior_en_3[2*m+1]),
.out_id(level_intpend_id_4[m]),
.out_priority(level_intpend_w_prior_en_4[m])) ;
end
assign claimid_in[ID_BITS-1:0] = level_intpend_id_4[0] ; // This is the last level output
assign selected_int_priority[INTPRIORITY_BITS-1:0] = level_intpend_w_prior_en_4[0] ;
`endif

31
configs/snapshots/default/pic_map_auto.h
View File

@ -1,31 +0,0 @@
// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }
always_comb begin
case (address[14:0])
15'b011000000000000 : mask[3:0] = 4'b0100;
15'b100000000000100 : mask[3:0] = 4'b1000;
15'b100000000001000 : mask[3:0] = 4'b1000;
15'b100000000001100 : mask[3:0] = 4'b1000;
15'b100000000010000 : mask[3:0] = 4'b1000;
15'b100000000010100 : mask[3:0] = 4'b1000;
15'b100000000011000 : mask[3:0] = 4'b1000;
15'b100000000011100 : mask[3:0] = 4'b1000;
15'b100000000100000 : mask[3:0] = 4'b1000;
15'b010000000000100 : mask[3:0] = 4'b0100;
15'b010000000001000 : mask[3:0] = 4'b0100;
15'b010000000001100 : mask[3:0] = 4'b0100;
15'b010000000010000 : mask[3:0] = 4'b0100;
15'b010000000010100 : mask[3:0] = 4'b0100;
15'b010000000011000 : mask[3:0] = 4'b0100;
15'b010000000011100 : mask[3:0] = 4'b0100;
15'b010000000100000 : mask[3:0] = 4'b0100;
15'b000000000000100 : mask[3:0] = 4'b0010;
15'b000000000001000 : mask[3:0] = 4'b0010;
15'b000000000001100 : mask[3:0] = 4'b0010;
15'b000000000010000 : mask[3:0] = 4'b0010;
15'b000000000010100 : mask[3:0] = 4'b0010;
15'b000000000011000 : mask[3:0] = 4'b0010;
15'b000000000011100 : mask[3:0] = 4'b0010;
15'b000000000100000 : mask[3:0] = 4'b0010;
default : mask[3:0] = 4'b0001;
endcase
end

395
configs/snapshots/default/whisper.json
View File

@ -1,395 +0,0 @@
{
"memmap" : {
"cosnoleio" : "0xd0580000"
},
"nmi_vec" : "0x11110000",
"dccm" : {
"region" : "0xf",
"offset" : "0x40000",
"size" : "0x10000"
},
"num_mmode_perf_regs" : "4",
"load_error_rollback" : "1",
"reset_vec" : "0x80000000",
"triggers" : [
{
"poke_mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
],
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
],
"mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
]
},
{
"poke_mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
],
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
],
"mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
]
},
{
"poke_mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
],
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
],
"mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
]
},
{
"poke_mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
],
"reset" : [
"0x23e00000",
"0x00000000",
"0x00000000"
],
"mask" : [
"0x081818c7",
"0xffffffff",
"0x00000000"
]
}
],
"xlen" : 32,
"pic" : {
"meigwctrl_offset" : "0x4000",
"region" : "0xf",
"total_int" : 8,
"size" : "0x8000",
"mpiccfg_offset" : "0x3000",
"meigwclr_offset" : "0x5000",
"total_int_plus1" : 9,
"meipt_offset" : "0x3004",
"int_words" : 1,
"meie_offset" : "0x2000",
"bits" : 15,
"meip_offset" : "0x1000",
"meipl_offset" : "0x0000",
"offset" : "0xc0000"
},
"store_error_rollback" : "0",
"even_odd_trigger_chains" : "true",
"max_mmode_perf_event" : "50",
"csr" : {
"pmpaddr9" : {
"exists" : "false"
},
"dicad1" : {
"reset" : "0x0",
"number" : "0x7ca",
"comment" : "Cache diagnostics.",
"debug" : "true",
"exists" : "true",
"mask" : "0x3"
},
"pmpcfg0" : {
"exists" : "false"
},
"mhpmcounter4h" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"dicago" : {
"reset" : "0x0",
"number" : "0x7cb",
"comment" : "Cache diagnostics.",
"debug" : "true",
"exists" : "true",
"mask" : "0x0"
},
"mie" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0x40000888"
},
"misa" : {
"reset" : "0x40001104",
"exists" : "true",
"mask" : "0x0"
},
"mhpmcounter6h" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"meicpct" : {
"reset" : "0x0",
"number" : "0xbca",
"comment" : "External claim id/priority capture.",
"exists" : "true",
"mask" : "0x0"
},
"mimpid" : {
"reset" : "0x1",
"exists" : "true",
"mask" : "0x0"
},
"mcpc" : {
"reset" : "0x0",
"number" : "0x7c2",
"exists" : "true",
"mask" : "0x0"
},
"mhpmevent4" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"pmpaddr8" : {
"exists" : "false"
},
"pmpcfg3" : {
"exists" : "false"
},
"marchid" : {
"reset" : "0x0000000b",
"exists" : "true",
"mask" : "0x0"
},
"pmpaddr5" : {
"exists" : "false"
},
"mfdc" : {
"reset" : "0x00070000",
"number" : "0x7f9",
"exists" : "true",
"mask" : "0x000707ff"
},
"mhpmevent6" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"mvendorid" : {
"reset" : "0x45",
"exists" : "true",
"mask" : "0x0"
},
"pmpaddr4" : {
"exists" : "false"
},
"dcsr" : {
"poke_mask" : "0x00008dcc",
"reset" : "0x40000003",
"exists" : "true",
"mask" : "0x00008c04"
},
"cycle" : {
"exists" : "false"
},
"pmpaddr12" : {
"exists" : "false"
},
"pmpaddr3" : {
"exists" : "false"
},
"mhpmcounter3h" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"time" : {
"exists" : "false"
},
"meicidpl" : {
"reset" : "0x0",
"number" : "0xbcb",
"comment" : "External interrupt claim id priority level.",
"exists" : "true",
"mask" : "0xf"
},
"pmpaddr14" : {
"exists" : "false"
},
"pmpaddr13" : {
"exists" : "false"
},
"pmpaddr1" : {
"exists" : "false"
},
"mhpmcounter6" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"dicad0" : {
"reset" : "0x0",
"number" : "0x7c9",
"comment" : "Cache diagnostics.",
"debug" : "true",
"exists" : "true",
"mask" : "0xffffffff"
},
"meipt" : {
"reset" : "0x0",
"number" : "0xbc9",
"comment" : "External interrupt priority threshold.",
"exists" : "true",
"mask" : "0xf"
},
"pmpaddr15" : {
"exists" : "false"
},
"mhpmcounter5" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"pmpcfg1" : {
"exists" : "false"
},
"pmpaddr10" : {
"exists" : "false"
},
"pmpaddr0" : {
"exists" : "false"
},
"pmpcfg2" : {
"exists" : "false"
},
"pmpaddr2" : {
"exists" : "false"
},
"mpmc" : {
"reset" : "0x0",
"number" : "0x7c6",
"comment" : "Core pause: Implemented as read only.",
"exists" : "true",
"mask" : "0x0"
},
"dmst" : {
"reset" : "0x0",
"number" : "0x7c4",
"comment" : "Memory synch trigger: Flush caches in debug mode.",
"debug" : "true",
"exists" : "true",
"mask" : "0x0"
},
"instret" : {
"exists" : "false"
},
"mhpmevent3" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"dicawics" : {
"reset" : "0x0",
"number" : "0x7c8",
"comment" : "Cache diagnostics.",
"debug" : "true",
"exists" : "true",
"mask" : "0x0130fffc"
},
"mip" : {
"poke_mask" : "0x40000888",
"reset" : "0x0",
"exists" : "true",
"mask" : "0x0"
},
"mhpmcounter5h" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"micect" : {
"reset" : "0x0",
"number" : "0x7f0",
"exists" : "true",
"mask" : "0xffffffff"
},
"miccmect" : {
"reset" : "0x0",
"number" : "0x7f1",
"exists" : "true",
"mask" : "0xffffffff"
},
"mhpmevent5" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"mhpmcounter3" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"pmpaddr6" : {
"exists" : "false"
},
"pmpaddr11" : {
"exists" : "false"
},
"mcgc" : {
"poke_mask" : "0x000001ff",
"reset" : "0x0",
"number" : "0x7f8",
"exists" : "true",
"mask" : "0x000001ff"
},
"mhpmcounter4" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0xffffffff"
},
"mdccmect" : {
"reset" : "0x0",
"number" : "0x7f2",
"exists" : "true",
"mask" : "0xffffffff"
},
"pmpaddr7" : {
"exists" : "false"
},
"meicurpl" : {
"reset" : "0x0",
"number" : "0xbcc",
"comment" : "External interrupt current priority level.",
"exists" : "true",
"mask" : "0xf"
},
"mstatus" : {
"reset" : "0x1800",
"exists" : "true",
"mask" : "0x88"
},
"tselect" : {
"reset" : "0x0",
"exists" : "true",
"mask" : "0x3"
}
},
"harts" : 1
}

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$RV_ROOT/workspace/work/snapshots/default/common_defines.vh
$RV_ROOT/design/include/def.sv
+incdir+$RV_ROOT/workspace/work/snapshots/default
+incdir+$RV_ROOT/design/lib
+incdir+$RV_ROOT/design/include
+incdir+$RV_ROOT/design/dmi
$RV_ROOT/design/swerv_wrapper.sv
$RV_ROOT/design/mem.sv
$RV_ROOT/design/pic_ctrl.sv
$RV_ROOT/design/swerv.sv
$RV_ROOT/design/dma_ctrl.sv
$RV_ROOT/design/ifu/ifu_aln_ctl.sv
$RV_ROOT/design/ifu/ifu_compress_ctl.sv
$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/ifu_bp_ctl.sv
$RV_ROOT/design/ifu/ifu_ic_mem.sv
$RV_ROOT/design/ifu/ifu_mem_ctl.sv
$RV_ROOT/design/ifu/ifu_iccm_mem.sv
$RV_ROOT/design/ifu/ifu.sv
$RV_ROOT/design/dec/dec_decode_ctl.sv
$RV_ROOT/design/dec/dec_gpr_ctl.sv
$RV_ROOT/design/dec/dec_ib_ctl.sv
$RV_ROOT/design/dec/dec_tlu_ctl.sv
$RV_ROOT/design/dec/dec_trigger.sv
$RV_ROOT/design/dec/dec.sv
$RV_ROOT/design/exu/exu_alu_ctl.sv
$RV_ROOT/design/exu/exu_mul_ctl.sv
$RV_ROOT/design/exu/exu_div_ctl.sv
$RV_ROOT/design/exu/exu.sv
$RV_ROOT/design/lsu/lsu.sv
$RV_ROOT/design/lsu/lsu_clkdomain.sv
$RV_ROOT/design/lsu/lsu_addrcheck.sv
$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/lsu_stbuf.sv
$RV_ROOT/design/lsu/lsu_bus_buffer.sv
$RV_ROOT/design/lsu/lsu_bus_intf.sv
$RV_ROOT/design/lsu/lsu_ecc.sv
$RV_ROOT/design/lsu/lsu_dccm_mem.sv
$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.sv
$RV_ROOT/design/lib/beh_lib.sv
$RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/svci_to_ahb.sv
$RV_ROOT/design/lib/ahb_to_svci.sv
$RV_ROOT/design/lib/svci_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_svci.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
// $Id$
//
// Owner:
// Function: SVCI to AXI4 Bridge
// Comments:
//
//********************************************************************************
module svci_to_axi4 #(parameter TAG = 1,
ID = 1,
PRTY = 1) (
input logic clk,
input logic rst_l,
input logic scan_mode,
input logic bus_clk_en,
input logic clk_override,
// AXI signals
// AXI Write Channels
output logic axi_awvalid,
input logic axi_awready,
output logic axi_awposted,
output logic [TAG-1:0] axi_awid,
output logic [31:0] axi_awaddr,
output logic [2:0] axi_awsize,
output logic [2:0] axi_awprot,
output logic [7:0] axi_awlen,
output logic [1:0] axi_awburst,
output logic [ID-1:0] axi_awmid,
output logic [PRTY-1:0] axi_awprty,
output logic axi_wvalid,
input logic axi_wready,
output logic [63:0] axi_wdata,
output logic [7:0] axi_wstrb,
output logic axi_wlast,
input logic axi_bvalid,
output logic axi_bready,
input logic axi_bposted,
input logic [1:0] axi_bresp,
input logic [TAG-1:0] axi_bid,
input logic [ID-1:0] axi_bmid,
input logic [PRTY-1:0] axi_bprty,
// AXI Read Channels
output logic axi_arvalid,
input logic axi_arready,
output logic [TAG-1:0] axi_arid,
output logic [31:0] axi_araddr,
output logic [2:0] axi_arsize,
output logic [2:0] axi_arprot,
output logic [7:0] axi_arlen,
output logic [1:0] axi_arburst,
output logic [ID-1:0] axi_armid,
output logic [PRTY-1:0] axi_arprty,
input logic axi_rvalid,
output logic axi_rready,
input logic [TAG-1:0] axi_rid,
input logic [63:0] axi_rdata,
input logic [1:0] axi_rresp,
input logic [ID-1:0] axi_rmid,
input logic [PRTY-1:0] axi_rprty,
// SVCI signals
input logic svci_cmd_valid,
output logic svci_cmd_ready,
input logic [TAG-1:0] svci_cmd_tag,
input logic [ID-1:0] svci_cmd_mid,
input logic [31:0] svci_cmd_addr,
input logic [63:0] svci_cmd_wdata,
input logic [7:0] svci_cmd_wbe,
input logic [2:0] svci_cmd_length,
input logic [2:0] svci_cmd_opc,
input logic [PRTY-1:0] svci_cmd_prty,
input logic dma_slv_algn_err,
output logic svci_rsp_valid,
input logic svci_rsp_ready,
output logic [TAG-1:0] svci_rsp_tag,
output logic [ID-1:0] svci_rsp_mid,
output logic [63:0] svci_rsp_rdata,
output logic [3:0] svci_rsp_opc,
output logic [PRTY-1:0] svci_rsp_prty
);
logic cmdbuf_wr_en, cmdbuf_data_en, cmdbuf_rst, cmdbuf_data_rst;
logic cmdbuf_full;
logic cmdbuf_vld, cmdbuf_data_vld;
logic [2:0] cmdbuf_opc, cmdbuf_size;
logic [7:0] cmdbuf_wstrb;
logic [31:0] cmdbuf_addr;
logic [63:0] cmdbuf_wdata;
logic [TAG-1:0] cmdbuf_tag;
logic [ID-1:0] cmdbuf_mid;
logic [PRTY-1:0] cmdbuf_prty;
logic wrbuf_en, wrbuf_rst;
logic wrbuf_vld;
logic wrbuf_posted;
logic [TAG-1:0] wrbuf_tag;
logic [ID-1:0] wrbuf_mid;
logic [1:0] wrbuf_resp;
logic [63:0] error_address; // SVCI needs the error address back on the rdata.
logic [PRTY-1:0] wrbuf_prty;
logic [1:0] axi_bresp_in; // need to map 2 errors in to 3 errors
logic bus_clk;
// Command buffer
assign cmdbuf_wr_en = svci_cmd_valid & svci_cmd_ready;
assign cmdbuf_data_en = cmdbuf_wr_en & (svci_cmd_opc[2:1] == 2'b01);
assign cmdbuf_rst = ((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en;
assign cmdbuf_data_rst = (axi_wvalid & axi_wready) & (cmdbuf_opc[2:1] == 2'b01) & ~cmdbuf_data_en;
assign cmdbuf_full = (cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready))) | (cmdbuf_data_vld & ~((axi_wvalid & axi_wready) & (cmdbuf_opc[2:1] == 2'b01)));
rvdffsc #(.WIDTH(1)) cmdbuf_vldff(.din(1'b1), .dout(cmdbuf_vld), .en(cmdbuf_wr_en), .clear(cmdbuf_rst), .clk(bus_clk), .*);
rvdffsc #(.WIDTH(1)) cmdbuf_data_vldff(.din(1'b1), .dout(cmdbuf_data_vld), .en(cmdbuf_data_en), .clear(cmdbuf_data_rst), .clk(bus_clk), .*);
rvdffs #(.WIDTH(3)) cmdbuf_opcff(.din(svci_cmd_opc[2:0]), .dout(cmdbuf_opc[2:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(3)) cmdbuf_sizeff(.din(svci_cmd_length[2:0]), .dout(cmdbuf_size[2:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
rvdffe #(.WIDTH(8)) cmdbuf_wstrbff(.din(svci_cmd_wbe[7:0]), .dout(cmdbuf_wstrb[7:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
rvdffe #(.WIDTH(32)) cmdbuf_addrff(.din(svci_cmd_addr[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
rvdffe #(.WIDTH(64)) cmdbuf_wdataff(.din(svci_cmd_wdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_data_en & bus_clk_en), .*);
rvdffs #(.WIDTH(TAG)) cmdbuf_tagff(.din(svci_cmd_tag[TAG-1:0]), .dout(cmdbuf_tag[TAG-1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(ID)) cmdbuf_midff(.din(svci_cmd_mid[ID-1:0]), .dout(cmdbuf_mid[ID-1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(PRTY)) cmdbuf_prtyff(.din(svci_cmd_prty[PRTY-1:0]), .dout(cmdbuf_prty[PRTY-1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
// AXI Write Channels
assign axi_awvalid = cmdbuf_vld & (cmdbuf_opc[2:1] == 2'b01);
assign axi_awposted = axi_awvalid & ~cmdbuf_opc[0];
assign axi_awid[TAG-1:0] = cmdbuf_tag[TAG-1:0];
assign axi_awaddr[31:0] = cmdbuf_addr[31:0];
assign axi_awsize[2:0] = cmdbuf_size[2:0];
assign axi_awprot[2:0] = 3'b0;
assign axi_awlen[7:0] = '0;
assign axi_awburst[1:0] = 2'b01;
assign axi_awmid = cmdbuf_mid[ID-1:0];
assign axi_awprty = cmdbuf_prty[PRTY-1:0];
assign axi_wvalid = cmdbuf_data_vld;
assign axi_wdata[63:0] = cmdbuf_wdata[63:0];
assign axi_wstrb[7:0] = cmdbuf_wstrb[7:0];
assign axi_wlast = 1'b1;
assign axi_bready = ~wrbuf_vld | svci_rsp_ready;
// AXI Read Channels
assign axi_arvalid = cmdbuf_vld & (cmdbuf_opc[2:0] == 3'b0);
assign axi_arid[TAG-1:0] = cmdbuf_tag[TAG-1:0];
assign axi_araddr[31:0] = cmdbuf_addr[31:0];
assign axi_arsize[2:0] = cmdbuf_size[2:0];
assign axi_arprot = 3'b0;
assign axi_arlen[7:0] = '0;
assign axi_arburst[1:0] = 2'b01;
assign axi_armid = cmdbuf_mid[ID-1:0];
assign axi_rready = ~wrbuf_vld & svci_rsp_ready;
assign axi_arprty = cmdbuf_prty[PRTY-1:0];
// SVCI_response signals
assign svci_rsp_valid = wrbuf_vld | axi_rvalid;
assign svci_rsp_tag[TAG-1:0] = wrbuf_vld ? wrbuf_tag[TAG-1:0] : axi_rid[TAG-1:0];
assign svci_rsp_mid[ID-1:0] = wrbuf_vld ? wrbuf_mid[ID-1:0] : axi_rmid[ID-1:0];
assign svci_rsp_rdata[63:0] = wrbuf_vld ? {32'b0, error_address[31:0]} : axi_rdata[63:0]; // rdata
assign svci_rsp_opc[3:2] = wrbuf_vld ? {1'b1, ~wrbuf_posted} : 2'b0;
// assign svci_rsp_opc[1:0] = wrbuf_vld ? {wrbuf_resp[1] ? (wrbuf_resp[0] ? 2'b10 : 2'b01) : 2'b0} : // AXI Slave Error -> SVCI Slave Error, AXI Decode Error -> SVCI Address Error
// {axi_rresp[1] ? (axi_rresp[0] ? 2'b10 : 2'b01) : 2'b0};
assign svci_rsp_opc[1:0] = wrbuf_vld ? wrbuf_resp[1:0] : // AXI Slave Error -> SVCI Slave Error, AXI Decode Error -> SVCI Address Error
{axi_rresp[1] ? (axi_rresp[0] ? 2'b10 : {dma_slv_algn_err, 1'b1}) : 2'b0};
assign svci_rsp_prty[PRTY-1:0] = wrbuf_vld ? wrbuf_prty[PRTY-1:0] : axi_rprty[PRTY-1:0];
assign svci_cmd_ready = ~cmdbuf_full;
// Write Response Buffer. Errors for writes need to send the Error address back on the rsp_rdata for SVCI. The address is sent back on axi_rdata bus for both reads and writes that have errors.
// assign wrbuf_en = axi_bvalid & svci_rsp_ready & (~axi_bposted | axi_bresp[1]);
assign wrbuf_en = axi_bvalid & axi_bready & (~axi_bposted | axi_bresp[1]);
assign wrbuf_rst = svci_rsp_valid & svci_rsp_ready & svci_rsp_opc[3] & ~wrbuf_en;
assign axi_bresp_in[1:0] = {axi_bresp[1] ? (axi_bresp[0] ? 2'b10 : {dma_slv_algn_err, 1'b1}) : 2'b0};
rvdffsc #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(bus_clk), .*);
rvdffs #(.WIDTH(32)) wrbuf_erroff (.din(axi_rdata[31:0]), .dout(error_address[31:0]), .en(wrbuf_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(1)) wrbuf_postedff(.din(axi_bposted), .dout(wrbuf_posted), .en(wrbuf_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(TAG)) wrbuf_tagff (.din(axi_bid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(ID)) wrbuf_midff (.din(axi_bmid[ID-1:0]), .dout(wrbuf_mid[ID-1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(PRTY))wrbuf_prtyff (.din(axi_bprty[PRTY-1:0]), .dout(wrbuf_prty[PRTY-1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
rvdffs #(.WIDTH(2)) wrbuf_respff (.din(axi_bresp_in[1:0]), .dout(wrbuf_resp[1:0]), .en(wrbuf_en), .clk(bus_clk), .*);
// Clock header logic
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
endmodule // svci_to_axi4

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cmark.c

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hello_world_dccm.ld

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
MEMORY {
EXTCODE : ORIGIN = 0, LENGTH = 0x10000
EXTDATA : ORIGIN = 0x10000, LENGTH = 0x10000
ICCM : ORIGIN = 0xee000000, LENGTH = 0x80000
DCCM : ORIGIN = 0xf0040000, LENGTH = 0x10000
}
SECTIONS {
.text_init : {*(.text_init)} > EXTCODE
init_end = .;
.data.ctl : AT(0xffec) { LONG(ADDR(.text)); LONG(text_end); LONG(LOADADDR(.text)); LONG(0xf0040000); LONG(STACK)}>EXTDATA
.text : AT(init_end) { *(.text) *(.text.startup)} > ICCM
text_end = .;
.data : AT(0x10000) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000;} > DCCM
}

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS {
.text : { *(.text*) }
_end = .;
. = 0xfff8;
.data.ctl : { LONG(0xf0040000); LONG(STACK) }
. = 0xf0040000;
.data : AT(0x10000) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000;}
}

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$RV_ROOT/design/swerv_wrapper.sv
$RV_ROOT/design/mem.sv
$RV_ROOT/design/pic_ctrl.sv
$RV_ROOT/design/swerv.sv
$RV_ROOT/design/dma_ctrl.sv
$RV_ROOT/design/ifu/ifu_aln_ctl.sv
$RV_ROOT/design/ifu/ifu_compress_ctl.sv
$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/ifu_bp_ctl.sv
$RV_ROOT/design/ifu/ifu_ic_mem.sv
$RV_ROOT/design/ifu/ifu_mem_ctl.sv
$RV_ROOT/design/ifu/ifu_iccm_mem.sv
$RV_ROOT/design/ifu/ifu.sv
$RV_ROOT/design/dec/dec_decode_ctl.sv
$RV_ROOT/design/dec/dec_gpr_ctl.sv
$RV_ROOT/design/dec/dec_ib_ctl.sv
$RV_ROOT/design/dec/dec_tlu_ctl.sv
$RV_ROOT/design/dec/dec_trigger.sv
$RV_ROOT/design/dec/dec.sv
$RV_ROOT/design/exu/exu_alu_ctl.sv
$RV_ROOT/design/exu/exu_mul_ctl.sv
$RV_ROOT/design/exu/exu_div_ctl.sv
$RV_ROOT/design/exu/exu.sv
$RV_ROOT/design/lsu/lsu.sv
$RV_ROOT/design/lsu/lsu_clkdomain.sv
$RV_ROOT/design/lsu/lsu_addrcheck.sv
$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/lsu_stbuf.sv
$RV_ROOT/design/lsu/lsu_bus_buffer.sv
$RV_ROOT/design/lsu/lsu_bus_intf.sv
$RV_ROOT/design/lsu/lsu_ecc.sv
$RV_ROOT/design/lsu/lsu_dccm_mem.sv
$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/lsu_trigger.sv
$RV_ROOT/design/dbg/dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.sv
-v $RV_ROOT/design/lib/beh_lib.sv
-v $RV_ROOT/design/lib/mem_lib.sv
-v $RV_ROOT/design/lib/ahb_to_axi4.sv
-v $RV_ROOT/design/lib/axi4_to_ahb.sv