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abstractaccelerator
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add soc for common test with soc.

This commit is contained in:
Colin 2022-01-17 11:53:50 +00:00
parent 3be1146718
commit 7aff1ae5f1
7 changed files with 18 additions and 17 deletions
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17
demo/helloworld/Makefile
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@ -12,6 +12,7 @@ TESTDIR = ${PWD}
BUILD_DIR = ${TESTDIR}/build BUILD_DIR = ${TESTDIR}/build
SWERV_CONFIG = ${TESTDIR}/swerv.config SWERV_CONFIG = ${TESTDIR}/swerv.config
RV_DESIGN = ${RV_ROOT}/design RV_DESIGN = ${RV_ROOT}/design
RV_SOC = ${RV_ROOT}/soc
TEST = hello_world TEST = hello_world
@ -25,8 +26,7 @@ LINK = $(TESTDIR)/link.ld
OFILES = $(TEST).o OFILES = $(TEST).o
OUTFILES = $(TEST).out OUTFILES = $(TEST).out
VPATH = $(BUILD_DIR) $(TESTDIR) SOCFILES = $(RV_SOC)/soc_top.sv $(RV_SOC)/ahb_sif.sv
TESTFILES = $(TESTDIR)/tb_top.sv $(TESTDIR)/ahb_sif.sv
defines = $(BUILD_DIR)/common_defines.vh ${RV_DESIGN}/include/swerv_types.sv defines = $(BUILD_DIR)/common_defines.vh ${RV_DESIGN}/include/swerv_types.sv
includes = -I${RV_DESIGN}/include -I${RV_DESIGN}/lib -I${BUILD_DIR} includes = -I${RV_DESIGN}/include -I${RV_DESIGN}/lib -I${BUILD_DIR}
@ -49,21 +49,22 @@ ${BUILD_DIR}/defines.h :
##################### Verilog Builds ##################################### ##################### Verilog Builds #####################################
verilator-build: ${TESTFILES} ${BUILD_DIR}/defines.h test_tb_top.cpp verilator-build: ${SOCFILES} ${BUILD_DIR}/defines.h test_soc_top.cpp
echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
$(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \ $(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \
-Wno-UNOPTFLAT \ -Wno-UNOPTFLAT \
-I${TESTDIR} \ -I${TESTDIR} \
-I${RV_SOC} \
-f ${TESTDIR}/flist \ -f ${TESTDIR}/flist \
${TESTFILES} \ ${SOCFILES} \
--top-module tb_top -exe test_tb_top.cpp --autoflush $(VERILATOR_DEBUG) --top-module soc_top -exe test_soc_top.cpp --autoflush $(VERILATOR_DEBUG)
cp ${TESTDIR}/test_tb_top.cpp obj_dir cp ${TESTDIR}/test_soc_top.cpp obj_dir
$(MAKE) -j -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS) $(MAKE) -j -C obj_dir/ -f Vsoc_top.mk $(VERILATOR_MAKE_FLAGS)
##################### Simulation Runs ##################################### ##################### Simulation Runs #####################################
verilator: program.hex verilator-build verilator: program.hex verilator-build
cd build && ../obj_dir/Vtb_top ${DEBUG_PLUS} cd build && ../obj_dir/Vsoc_top ${DEBUG_PLUS}
##################### Test Build ##################################### ##################### Test Build #####################################

2
demo/helloworld/swerv.config
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@ -854,7 +854,7 @@ our %config = (#{{{
"pic_meigwclr_count" => $pic_total_int "pic_meigwclr_count" => $pic_total_int
}, },
"testbench" => { "testbench" => {
"TOP" => "tb_top", "TOP" => "soc_top",
"RV_TOP" => "`TOP.rvtop", "RV_TOP" => "`TOP.rvtop",
"CPU_TOP" => "`RV_TOP.swerv", "CPU_TOP" => "`RV_TOP.swerv",
"clock_period" => "100", "clock_period" => "100",

10
demo/helloworld/test_tb_top.cpp → demo/helloworld/test_soc_top.cpp
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@ -17,7 +17,7 @@
#include <iostream> #include <iostream>
#include <utility> #include <utility>
#include <string> #include <string>
#include "Vtb_top.h" #include "Vsoc_top.h"
#include "verilated.h" #include "verilated.h"
#include "verilated_vcd_c.h" #include "verilated_vcd_c.h"
@ -34,7 +34,7 @@ int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Vtb_top* tb = new Vtb_top; Vsoc_top* soc = new Vsoc_top;
// init trace dump // init trace dump
VerilatedVcdC* tfp = NULL; VerilatedVcdC* tfp = NULL;
@ -42,7 +42,7 @@ int main(int argc, char** argv) {
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); Verilated::traceEverOn(true);
tfp = new VerilatedVcdC; tfp = new VerilatedVcdC;
tb->trace (tfp, 24); soc->trace (tfp, 24);
tfp->open ("sim.vcd"); tfp->open ("sim.vcd");
#endif #endif
// Simulate // Simulate
@ -51,8 +51,8 @@ int main(int argc, char** argv) {
tfp->dump (main_time); tfp->dump (main_time);
#endif #endif
main_time += 5; main_time += 5;
tb->core_clk = !tb->core_clk; soc->core_clk = !soc->core_clk;
tb->eval(); soc->eval();
} }
#if VM_TRACE #if VM_TRACE

0
demo/helloworld/ahb_sif.sv → soc/ahb_sif.sv
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0
demo/helloworld/axi_lsu_dma_bridge.sv → soc/axi_lsu_dma_bridge.sv
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0
demo/helloworld/dasm.svi → soc/dasm.svi
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6
demo/helloworld/tb_top.sv → soc/soc_top.sv
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@ -14,9 +14,9 @@
// limitations under the License. // limitations under the License.
// //
`ifdef VERILATOR `ifdef VERILATOR
module tb_top ( input bit core_clk); module soc_top ( input bit core_clk);
`else `else
module tb_top; module soc_top;
bit core_clk; bit core_clk;
`endif `endif
logic rst_l; logic rst_l;
@ -373,7 +373,7 @@ module tb_top;
end end
if(`DEC.dec_nonblock_load_wen) begin if(`DEC.dec_nonblock_load_wen) begin
$fwrite (el, "%10d : %10d%22s=%h ; nbL\n", cycleCnt, 0, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data); $fwrite (el, "%10d : %10d%22s=%h ; nbL\n", cycleCnt, 0, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
tb_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data; soc_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
end end
end end