add soc for common test with soc.

demo/helloworld/Makefile

@@ -12,6 +12,7 @@ TESTDIR = ${PWD}
 BUILD_DIR = ${TESTDIR}/build
 SWERV_CONFIG = ${TESTDIR}/swerv.config
 RV_DESIGN = ${RV_ROOT}/design
+RV_SOC = ${RV_ROOT}/soc
 
 TEST = hello_world
 
@@ -25,8 +26,7 @@ LINK = $(TESTDIR)/link.ld
 OFILES = $(TEST).o
 OUTFILES = $(TEST).out
 
-VPATH = $(BUILD_DIR) $(TESTDIR)
-TESTFILES = $(TESTDIR)/tb_top.sv $(TESTDIR)/ahb_sif.sv
+SOCFILES = $(RV_SOC)/soc_top.sv $(RV_SOC)/ahb_sif.sv
 
 defines = $(BUILD_DIR)/common_defines.vh ${RV_DESIGN}/include/swerv_types.sv
 includes = -I${RV_DESIGN}/include -I${RV_DESIGN}/lib  -I${BUILD_DIR}
@@ -49,21 +49,22 @@ ${BUILD_DIR}/defines.h :
 
 ##################### Verilog Builds #####################################
 
-verilator-build: ${TESTFILES} ${BUILD_DIR}/defines.h test_tb_top.cpp
+verilator-build: ${SOCFILES} ${BUILD_DIR}/defines.h test_soc_top.cpp
 	echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
 	$(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \
 	              -Wno-UNOPTFLAT \
 	              -I${TESTDIR} \
+	              -I${RV_SOC} \
 		            -f ${TESTDIR}/flist \
-	              ${TESTFILES} \
-	              --top-module tb_top -exe test_tb_top.cpp --autoflush $(VERILATOR_DEBUG)
-	cp ${TESTDIR}/test_tb_top.cpp obj_dir
-	$(MAKE) -j -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)
+	              ${SOCFILES} \
+	              --top-module soc_top -exe test_soc_top.cpp --autoflush $(VERILATOR_DEBUG)
+	cp ${TESTDIR}/test_soc_top.cpp obj_dir
+	$(MAKE) -j -C obj_dir/ -f Vsoc_top.mk $(VERILATOR_MAKE_FLAGS)
 
 ##################### Simulation Runs #####################################
 
 verilator: program.hex verilator-build
-	cd build && ../obj_dir/Vtb_top ${DEBUG_PLUS}
+	cd build && ../obj_dir/Vsoc_top ${DEBUG_PLUS}
 
 ##################### Test Build #####################################
 

demo/helloworld/swerv.config

@@ -854,7 +854,7 @@ our %config = (#{{{
         "pic_meigwclr_count"  => $pic_total_int
     },
     "testbench" => {
-        "TOP"               => "tb_top",
+        "TOP"               => "soc_top",
         "RV_TOP"            => "`TOP.rvtop",
         "CPU_TOP"            => "`RV_TOP.swerv",
         "clock_period"      => "100",

demo/helloworld/test_soc_top.cpp

@@ -17,7 +17,7 @@
 #include <iostream>
 #include <utility>
 #include <string>
-#include "Vtb_top.h"
+#include "Vsoc_top.h"
 #include "verilated.h"
 #include "verilated_vcd_c.h"
 
@@ -34,7 +34,7 @@ int main(int argc, char** argv) {
 
   Verilated::commandArgs(argc, argv);
 
-  Vtb_top* tb = new Vtb_top;
+  Vsoc_top* soc = new Vsoc_top;
 
   // init trace dump
   VerilatedVcdC* tfp = NULL;
@@ -42,7 +42,7 @@ int main(int argc, char** argv) {
 #if VM_TRACE
   Verilated::traceEverOn(true);
   tfp = new VerilatedVcdC;
-  tb->trace (tfp, 24);
+  soc->trace (tfp, 24);
   tfp->open ("sim.vcd");
 #endif
   // Simulate
@@ -51,8 +51,8 @@ int main(int argc, char** argv) {
       tfp->dump (main_time);
 #endif
       main_time += 5;
-      tb->core_clk = !tb->core_clk;
-      tb->eval();
+      soc->core_clk = !soc->core_clk;
+      soc->eval();
   }
 
 #if VM_TRACE

soc/soc_top.sv

@@ -14,9 +14,9 @@
 // limitations under the License.
 //
 `ifdef VERILATOR
-module tb_top ( input bit core_clk);
+module soc_top ( input bit core_clk);
 `else
-module tb_top;
+module soc_top;
     bit                         core_clk;
 `endif
     logic                       rst_l;
@@ -373,7 +373,7 @@ module tb_top;
         end
         if(`DEC.dec_nonblock_load_wen) begin
             $fwrite (el, "%10d : %10d%22s=%h ; nbL\n", cycleCnt, 0, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
-            tb_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
+            soc_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
         end
     end