From 7ff8d7fb5a23a31045b6d92a70ea5f925dbcac46 Mon Sep 17 00:00:00 2001 From: Joseph Rahmeh Date: Tue, 13 Aug 2019 12:48:48 -0700 Subject: [PATCH] Untabified files. --- design/dbg/dbg.sv | 96 +-- design/dec/dec.sv | 192 +++--- design/dec/dec_decode_ctl.sv | 1122 ++++++++++++++++---------------- design/dec/dec_gpr_ctl.sv | 12 +- design/dec/dec_ib_ctl.sv | 168 ++--- design/dec/dec_tlu_ctl.sv | 732 ++++++++++----------- design/dec/dec_trigger.sv | 6 +- design/dma_ctrl.sv | 32 +- design/ifu/ifu.sv | 90 +-- design/ifu/ifu_aln_ctl.sv | 900 ++++++++++++------------- design/ifu/ifu_bp_ctl.sv | 908 +++++++++++++------------- design/ifu/ifu_compress_ctl.sv | 64 +- design/ifu/ifu_ic_mem.sv | 62 +- design/ifu/ifu_iccm_mem.sv | 38 +- design/ifu/ifu_ifc_ctl.sv | 132 ++-- design/ifu/ifu_mem_ctl.sv | 80 +-- design/include/swerv_types.sv | 466 ++++++------- design/lib/ahb_to_axi4.sv | 26 +- design/lib/axi4_to_ahb.sv | 32 +- design/lib/beh_lib.sv | 154 ++--- design/lib/mem_lib.sv | 246 +++---- design/lsu/lsu.sv | 2 +- design/lsu/lsu_addrcheck.sv | 20 +- design/lsu/lsu_bus_buffer.sv | 10 +- design/lsu/lsu_bus_intf.sv | 22 +- design/lsu/lsu_dccm_ctl.sv | 8 +- design/lsu/lsu_dccm_mem.sv | 14 +- design/lsu/lsu_ecc.sv | 28 +- design/lsu/lsu_stbuf.sv | 70 +- design/lsu/lsu_trigger.sv | 6 +- design/mem.sv | 8 +- design/pic_ctrl.sv | 14 +- design/swerv.sv | 190 +++--- design/swerv_wrapper.sv | 124 ++-- testbench/tb_top.sv | 10 +- 35 files changed, 3042 insertions(+), 3042 deletions(-) diff --git a/design/dbg/dbg.sv b/design/dbg/dbg.sv index 859c1dc..c6cdbd2 100644 --- a/design/dbg/dbg.sv +++ b/design/dbg/dbg.sv @@ -121,7 +121,7 @@ module dbg ( state_t dbg_state; state_t dbg_nxtstate; - logic dbg_state_en; + logic dbg_state_en; // these are the registers that the debug module implements logic [31:0] dmstatus_reg; // [26:24]-dmerr, [17:16]-resume ack, [9:8]-halted, [3:0]-version logic [31:0] dmcontrol_reg; // dmcontrol register has only 6 bits implemented. 31: haltreq, 30: resumereq, 29: haltreset, 28: ackhavereset, 1: ndmreset, 0: dmactive. @@ -167,13 +167,13 @@ module dbg ( //System bus section logic sbcs_wren; - logic sbcs_sbbusy_wren; + logic sbcs_sbbusy_wren; logic sbcs_sbbusy_din; - logic sbcs_sbbusyerror_wren; + logic sbcs_sbbusyerror_wren; logic sbcs_sbbusyerror_din; logic sbcs_sberror_wren; - logic [2:0] sbcs_sberror_din; + logic [2:0] sbcs_sberror_din; logic sbcs_unaligned; logic sbcs_illegal_size; @@ -192,7 +192,7 @@ module dbg ( logic sbaddress0_reg_wren1; logic sbaddress0_reg_wren; logic [31:0] sbaddress0_reg_din; - logic [3:0] sbaddress0_incr; + logic [3:0] sbaddress0_incr; logic sbreadonaddr_access; logic sbreadondata_access; logic sbdata0wr_access; @@ -268,8 +268,8 @@ module dbg ( assign sbaddress0_incr[3:0] = ({4{(sbcs_reg[19:17] == 3'b000)}} & 4'b0001) | ({4{(sbcs_reg[19:17] == 3'b001)}} & 4'b0010) | - ({4{(sbcs_reg[19:17] == 3'b010)}} & 4'b0100) | - ({4{(sbcs_reg[19:17] == 3'b100)}} & 4'b1000); + ({4{(sbcs_reg[19:17] == 3'b010)}} & 4'b0100) | + ({4{(sbcs_reg[19:17] == 3'b100)}} & 4'b1000); // sbdata //assign sbdata0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 32'h3c); @@ -350,7 +350,7 @@ module dbg ( assign abstractcs_error_sel4 = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & ( ((dmi_reg_wdata[22:20] == 3'b001) & data1_reg[0]) | ((dmi_reg_wdata[22:20] == 3'b010) & (|data1_reg[1:0])) | - dmi_reg_wdata[22] | (dmi_reg_wdata[22:20] == 3'b011) + dmi_reg_wdata[22] | (dmi_reg_wdata[22:20] == 3'b011) ); assign abstractcs_error_sel5 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en; @@ -361,7 +361,7 @@ module dbg ( ({3{abstractcs_error_sel1}} & 3'b010) | // writing a non-zero command to cmd field of command ({3{abstractcs_error_sel2}} & 3'b011) | // exception while running command ({3{abstractcs_error_sel3}} & 3'b100) | // writing a comnand when not in the halted state - ({3{abstractcs_error_sel4}} & 3'b111) | // unaligned abstract memory command + ({3{abstractcs_error_sel4}} & 3'b111) | // unaligned abstract memory command ({3{abstractcs_error_sel5}} & ~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) | // W1C ({3{~abstractcs_error_selor}} & abstractcs_reg[10:8]); // hold @@ -414,37 +414,37 @@ module dbg ( HALTING : begin dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK dbg_state_en = dmstatus_reg[9]; // core indicates halted - end + end HALTED: begin // wait for halted to go away before send to resume. Else start of new command dbg_nxtstate = (dmstatus_reg[9] & ~dmcontrol_reg[1]) ? ((dmcontrol_reg[30] & ~dmcontrol_reg[31]) ? RESUMING : CMD_START) : (dmcontrol_reg[31] ? HALTING : IDLE); // This is MPC halted case //dbg_nxtstate = dmcontrol_reg[1] ? IDLE : (dmcontrol_reg[30] & ~dmcontrol_reg[31]) ? RESUMING : CMD_START; // wait for halted to go away before send to resume. Else start of new command - dbg_state_en = (dmstatus_reg[9] & dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q) | command_wren | dmcontrol_reg[1] | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only); + dbg_state_en = (dmstatus_reg[9] & dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q) | command_wren | dmcontrol_reg[1] | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only); abstractcs_busy_wren = dbg_state_en & (dbg_nxtstate == CMD_START); // write busy when a new command was written by jtag abstractcs_busy_din = 1'b1; dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming - end + end CMD_START: begin dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : CMD_WAIT; // new command sent to the core dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]); - end + end CMD_WAIT: begin dbg_nxtstate = CMD_DONE; dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command end - CMD_DONE: begin + CMD_DONE: begin dbg_nxtstate = HALTED; dbg_state_en = 1'b1; - abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 ) + abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 ) abstractcs_busy_din = 1'b0; end - RESUMING : begin - dbg_nxtstate = IDLE; + RESUMING : begin + dbg_nxtstate = IDLE; dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register end default : begin - dbg_nxtstate = IDLE; + dbg_nxtstate = IDLE; dbg_state_en = 1'b0; abstractcs_busy_wren = 1'b0; abstractcs_busy_din = 1'b0; @@ -461,7 +461,7 @@ module dbg ( ({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) | ({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) | ({32{dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0]) | - ({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) | + ({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) | ({32{dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0]) | ({32{dmi_reg_addr == 7'h3c}} & sbdata0_reg[31:0]) | ({32{dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]); @@ -495,58 +495,58 @@ module dbg ( case (sb_state) SBIDLE: begin sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD; - sb_state_en = sbdata0wr_access | sbreadondata_access | sbreadonaddr_access; - sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command - sbcs_sbbusy_din = 1'b1; + sb_state_en = sbdata0wr_access | sbreadondata_access | sbreadonaddr_access; + sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command + sbcs_sbbusy_din = 1'b1; sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits - sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; + sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; end WAIT_RD: begin sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD; sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size; sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; - sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; + sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; end WAIT_WR: begin sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR; sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size; sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; - sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; + sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; end - CMD_RD : begin - sb_nxtstate = RSP_RD; + CMD_RD : begin + sb_nxtstate = RSP_RD; sb_state_en = sb_axi_arvalid_q & sb_axi_arready_q & dbg_bus_clk_en; - end - CMD_WR : begin - sb_nxtstate = (sb_axi_awready_q & sb_axi_wready_q) ? RSP_WR : (sb_axi_awready_q ? CMD_WR_DATA : CMD_WR_ADDR); + end + CMD_WR : begin + sb_nxtstate = (sb_axi_awready_q & sb_axi_wready_q) ? RSP_WR : (sb_axi_awready_q ? CMD_WR_DATA : CMD_WR_ADDR); sb_state_en = ((sb_axi_awvalid_q & sb_axi_awready_q) | (sb_axi_wvalid_q & sb_axi_wready_q)) & dbg_bus_clk_en; - end - CMD_WR_ADDR : begin - sb_nxtstate = RSP_WR; + end + CMD_WR_ADDR : begin + sb_nxtstate = RSP_WR; sb_state_en = sb_axi_awvalid_q & sb_axi_awready_q & dbg_bus_clk_en; - end - CMD_WR_DATA : begin - sb_nxtstate = RSP_WR; + end + CMD_WR_DATA : begin + sb_nxtstate = RSP_WR; sb_state_en = sb_axi_wvalid_q & sb_axi_wready_q & dbg_bus_clk_en; - end - RSP_RD: begin + end + RSP_RD: begin sb_nxtstate = DONE; - sb_state_en = sb_axi_rvalid_q & sb_axi_rready_q & dbg_bus_clk_en; + sb_state_en = sb_axi_rvalid_q & sb_axi_rready_q & dbg_bus_clk_en; sbcs_sberror_wren = sb_state_en & sb_axi_rresp_q[1]; - sbcs_sberror_din[2:0] = 3'b010; - end - RSP_WR: begin + sbcs_sberror_din[2:0] = 3'b010; + end + RSP_WR: begin sb_nxtstate = DONE; - sb_state_en = sb_axi_bvalid_q & sb_axi_bready_q & dbg_bus_clk_en; + sb_state_en = sb_axi_bvalid_q & sb_axi_bready_q & dbg_bus_clk_en; sbcs_sberror_wren = sb_state_en & sb_axi_bresp_q[1]; - sbcs_sberror_din[2:0] = 3'b010; - end - DONE: begin + sbcs_sberror_din[2:0] = 3'b010; + end + DONE: begin sb_nxtstate = SBIDLE; sb_state_en = 1'b1; - sbcs_sbbusy_wren = 1'b1; // reset the single read + sbcs_sbbusy_wren = 1'b1; // reset the single read sbcs_sbbusy_din = 1'b0; - sbaddress0_reg_wren1 = sbcs_reg[16]; // auto increment was set. Update to new address after completing the current command + sbaddress0_reg_wren1 = sbcs_reg[16]; // auto increment was set. Update to new address after completing the current command end default : begin sb_nxtstate = SBIDLE; diff --git a/design/dec/dec.sv b/design/dec/dec.sv index 6062163..e4c1de1 100644 --- a/design/dec/dec.sv +++ b/design/dec/dec.sv @@ -41,7 +41,7 @@ module dec input logic [31:1] rst_vec, // reset vector, from core pins input logic nmi_int, // NMI pin - input logic [31:1] nmi_vec, // NMI vector, from pins + input logic [31:1] nmi_vec, // NMI vector, from pins input logic i_cpu_halt_req, // Asynchronous Halt request to CPU input logic i_cpu_run_req, // Asynchronous Restart request to CPU @@ -66,17 +66,17 @@ module dec input logic exu_pmu_i0_br_misp, // slot 0 branch misp input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken input logic exu_pmu_i0_pc4, // slot 0 4 byte branch - input logic exu_pmu_i1_br_misp, // slot 1 branch misp + input logic exu_pmu_i1_br_misp, // slot 1 branch misp input logic exu_pmu_i1_br_ataken, // slot 1 branch actual taken input logic exu_pmu_i1_pc4, // slot 1 4 byte branch - input logic lsu_nonblock_load_valid_dc3, // valid nonblock load at dc3 - input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // -> corresponding tag - input logic lsu_nonblock_load_inv_dc5, // invalidate request for nonblock load dc5 - input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // -> corresponding tag - input logic lsu_nonblock_load_data_valid, // valid nonblock load data back - input logic lsu_nonblock_load_data_error, // nonblock load bus error + input logic lsu_nonblock_load_valid_dc3, // valid nonblock load at dc3 + input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // -> corresponding tag + input logic lsu_nonblock_load_inv_dc5, // invalidate request for nonblock load dc5 + input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // -> corresponding tag + input logic lsu_nonblock_load_data_valid, // valid nonblock load data back + input logic lsu_nonblock_load_data_error, // nonblock load bus error input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag input logic [31:0] lsu_nonblock_load_data, // nonblock load data @@ -104,15 +104,15 @@ module dec input logic [1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i - input logic ifu_i0_icaf, // icache access fault - input logic ifu_i1_icaf, + input logic ifu_i0_icaf, // icache access fault + input logic ifu_i1_icaf, input logic ifu_i0_icaf_f1, // i0 has access fault on second fetch group input logic ifu_i1_icaf_f1, - input logic ifu_i0_perr, // icache parity error - input logic ifu_i1_perr, - input logic ifu_i0_sbecc, // icache/iccm single-bit error - input logic ifu_i1_sbecc, - input logic ifu_i0_dbecc, // icache/iccm double-bit error + input logic ifu_i0_perr, // icache parity error + input logic ifu_i1_perr, + input logic ifu_i0_sbecc, // icache/iccm single-bit error + input logic ifu_i1_sbecc, + input logic ifu_i0_dbecc, // icache/iccm double-bit error input logic ifu_i1_dbecc, input logic lsu_freeze_dc3, // freeze pipe: decode -> dc3 @@ -168,7 +168,7 @@ module dec input logic [31:0] exu_i1_result_e4, - input logic ifu_i0_valid, ifu_i1_valid, // fetch valids to instruction buffer + input logic ifu_i0_valid, ifu_i1_valid, // fetch valids to instruction buffer input logic [31:0] ifu_i0_instr, ifu_i1_instr, // fetch inst's to instruction buffer input logic [31:1] ifu_i0_pc, ifu_i1_pc, // pc's for instruction buffer input logic ifu_i0_pc4, ifu_i1_pc4, // indication of 4B or 2B for corresponding inst @@ -245,42 +245,42 @@ module dec `ifdef RV_BTB_48 input logic [1:0] exu_i1_br_way_e4, // way hit or repl input logic [1:0] exu_i0_br_way_e4, // way hit or repl -`else +`else input logic exu_i1_br_way_e4, // way hit or repl input logic exu_i0_br_way_e4, // way hit or repl -`endif - +`endif + output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data - output logic [31:0] gpr_i1_rs1_d, - output logic [31:0] gpr_i1_rs2_d, - + output logic [31:0] gpr_i1_rs1_d, + output logic [31:0] gpr_i1_rs2_d, + output logic [31:0] dec_i0_immed_d, // immediate data - output logic [31:0] dec_i1_immed_d, - + output logic [31:0] dec_i1_immed_d, + output logic [12:1] dec_i0_br_immed_d, // br immediate data output logic [12:1] dec_i1_br_immed_d, - - output alu_pkt_t i0_ap, // alu packet - output alu_pkt_t i1_ap, + + output alu_pkt_t i0_ap, // alu packet + output alu_pkt_t i1_ap, - output logic dec_i0_alu_decode_d, // alu schedule on primary alu - output logic dec_i1_alu_decode_d, + output logic dec_i0_alu_decode_d, // alu schedule on primary alu + output logic dec_i1_alu_decode_d, - output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's - output logic dec_i1_select_pc_d, + output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's + output logic dec_i1_select_pc_d, output logic [31:1] dec_i0_pc_d, dec_i1_pc_d, // pc's at decode - output logic dec_i0_rs1_bypass_en_d, // rs1 bypass enable - output logic dec_i0_rs2_bypass_en_d, // rs2 bypass enable - output logic dec_i1_rs1_bypass_en_d, - output logic dec_i1_rs2_bypass_en_d, + output logic dec_i0_rs1_bypass_en_d, // rs1 bypass enable + output logic dec_i0_rs2_bypass_en_d, // rs2 bypass enable + output logic dec_i1_rs1_bypass_en_d, + output logic dec_i1_rs2_bypass_en_d, output logic [31:0] i0_rs1_bypass_data_d, // rs1 bypass data output logic [31:0] i0_rs2_bypass_data_d, // rs2 bypass data output logic [31:0] i1_rs1_bypass_data_d, output logic [31:0] i1_rs2_bypass_data_d, - output logic dec_ib3_valid_d, // ib3 buffer valid + output logic dec_ib3_valid_d, // ib3 buffer valid output logic dec_ib2_valid_d, // ib2 buffer valid output lsu_pkt_t lsu_p, // lsu packet @@ -402,29 +402,29 @@ module dec logic dec_tlu_dec_clk_override; // to and from dec blocks logic clk_override; - logic dec_ib1_valid_d; - logic dec_ib0_valid_d; + logic dec_ib1_valid_d; + logic dec_ib0_valid_d; - logic [1:0] dec_pmu_instr_decoded; - logic dec_pmu_decode_stall; - logic dec_pmu_presync_stall; - logic dec_pmu_postsync_stall; + logic [1:0] dec_pmu_instr_decoded; + logic dec_pmu_decode_stall; + logic dec_pmu_presync_stall; + logic dec_pmu_postsync_stall; logic dec_tlu_wr_pause_wb; // CSR write to pause reg is at WB. - logic dec_i0_rs1_en_d; - logic dec_i0_rs2_en_d; + logic dec_i0_rs1_en_d; + logic dec_i0_rs2_en_d; logic dec_fence_pending; // tell TLU to stall DMA - logic [4:0] dec_i0_rs1_d; - logic [4:0] dec_i0_rs2_d; + logic [4:0] dec_i0_rs1_d; + logic [4:0] dec_i0_rs2_d; - logic dec_i1_rs1_en_d; - logic dec_i1_rs2_en_d; + logic dec_i1_rs1_en_d; + logic dec_i1_rs2_en_d; - logic [4:0] dec_i1_rs1_d; - logic [4:0] dec_i1_rs2_d; + logic [4:0] dec_i1_rs1_d; + logic [4:0] dec_i1_rs2_d; logic [31:0] dec_i0_instr_d, dec_i1_instr_d; @@ -433,12 +433,12 @@ module dec logic dec_tlu_dual_issue_disable; - logic [4:0] dec_i0_waddr_wb; - logic dec_i0_wen_wb; + logic [4:0] dec_i0_waddr_wb; + logic dec_i0_wen_wb; logic [31:0] dec_i0_wdata_wb; - logic [4:0] dec_i1_waddr_wb; - logic dec_i1_wen_wb; + logic [4:0] dec_i1_waddr_wb; + logic dec_i1_wen_wb; logic [31:0] dec_i1_wdata_wb; logic dec_csr_wen_wb; // csr write enable at wb @@ -448,7 +448,7 @@ module dec logic [31:0] dec_csr_wrdata_wb; // csr write data at wb logic [31:0] dec_csr_rddata_d; // csr read data at wb - logic dec_csr_legal_d; // csr indicates legal operation + logic dec_csr_legal_d; // csr indicates legal operation logic dec_csr_wen_unq_d; // valid csr with write - for csr legal logic dec_csr_any_unq_d; // valid csr - for csr legal @@ -458,10 +458,10 @@ module dec trap_pkt_t dec_tlu_packet_e4; - logic dec_i0_pc4_d, dec_i1_pc4_d; - logic dec_tlu_presync_d; - logic dec_tlu_postsync_d; - logic dec_tlu_debug_stall; + logic dec_i0_pc4_d, dec_i1_pc4_d; + logic dec_tlu_presync_d; + logic dec_tlu_postsync_d; + logic dec_tlu_debug_stall; logic [31:0] dec_illegal_inst; @@ -470,33 +470,33 @@ module dec logic wen_bank_id; logic [GPR_BANKS_LOG2-1:0] wr_bank_id; - logic dec_i0_icaf_d; - logic dec_i1_icaf_d; - logic dec_i0_perr_d; - logic dec_i1_perr_d; - logic dec_i0_sbecc_d; - logic dec_i1_sbecc_d; - logic dec_i0_dbecc_d; - logic dec_i1_dbecc_d; + logic dec_i0_icaf_d; + logic dec_i1_icaf_d; + logic dec_i0_perr_d; + logic dec_i1_perr_d; + logic dec_i0_sbecc_d; + logic dec_i1_sbecc_d; + logic dec_i0_dbecc_d; + logic dec_i1_dbecc_d; - logic dec_i0_icaf_f1_d; + logic dec_i0_icaf_f1_d; - logic dec_i0_decode_d; - logic dec_i1_decode_d; + logic dec_i0_decode_d; + logic dec_i1_decode_d; - logic [3:0] dec_i0_trigger_match_d; - logic [3:0] dec_i1_trigger_match_d; + logic [3:0] dec_i0_trigger_match_d; + logic [3:0] dec_i1_trigger_match_d; - logic dec_debug_fence_d; + logic dec_debug_fence_d; - logic dec_nonblock_load_wen; - logic [4:0] dec_nonblock_load_waddr; - logic dec_tlu_flush_pause_wb; + logic dec_nonblock_load_wen; + logic [4:0] dec_nonblock_load_waddr; + logic dec_tlu_flush_pause_wb; - logic dec_i0_load_e4; + logic dec_i0_load_e4; - logic dec_pause_state; + logic dec_pause_state; br_pkt_t dec_i0_brp; br_pkt_t dec_i1_brp; @@ -507,7 +507,7 @@ module dec assign dec_dbg_rddata[31:0] = dec_i0_wdata_wb[31:0]; dec_ib_ctl instbuff (.* - ); + ); dec_decode_ctl decode (.*); @@ -521,20 +521,20 @@ module dec dec_gpr_ctl #(.GPR_BANKS(GPR_BANKS), .GPR_BANKS_LOG2(GPR_BANKS_LOG2)) arf (.*, - // inputs + // inputs .raddr0(dec_i0_rs1_d[4:0]), .rden0(dec_i0_rs1_en_d), .raddr1(dec_i0_rs2_d[4:0]), .rden1(dec_i0_rs2_en_d), .raddr2(dec_i1_rs1_d[4:0]), .rden2(dec_i1_rs1_en_d), .raddr3(dec_i1_rs2_d[4:0]), .rden3(dec_i1_rs2_en_d), - - .waddr0(dec_i0_waddr_wb[4:0]), .wen0(dec_i0_wen_wb), .wd0(dec_i0_wdata_wb[31:0]), - .waddr1(dec_i1_waddr_wb[4:0]), .wen1(dec_i1_wen_wb), .wd1(dec_i1_wdata_wb[31:0]), - .waddr2(dec_nonblock_load_waddr[4:0]), .wen2(dec_nonblock_load_wen), .wd2(lsu_nonblock_load_data[31:0]), - - // outputs + + .waddr0(dec_i0_waddr_wb[4:0]), .wen0(dec_i0_wen_wb), .wd0(dec_i0_wdata_wb[31:0]), + .waddr1(dec_i1_waddr_wb[4:0]), .wen1(dec_i1_wen_wb), .wd1(dec_i1_wdata_wb[31:0]), + .waddr2(dec_nonblock_load_waddr[4:0]), .wen2(dec_nonblock_load_wen), .wd2(lsu_nonblock_load_data[31:0]), + + // outputs .rd0(gpr_i0_rs1_d[31:0]), .rd1(gpr_i0_rs2_d[31:0]), .rd2(gpr_i1_rs1_d[31:0]), .rd3(gpr_i1_rs2_d[31:0]) - ); + ); // Trigger @@ -543,19 +543,19 @@ module dec - + // trace logic [15:0] dec_i0_cinst_d; logic [15:0] dec_i1_cinst_d; - logic [31:0] dec_i0_inst_wb1; - logic [31:0] dec_i1_inst_wb1; - logic [31:1] dec_i0_pc_wb1; - logic [31:1] dec_i1_pc_wb1; + logic [31:0] dec_i0_inst_wb1; + logic [31:0] dec_i1_inst_wb1; + logic [31:1] dec_i0_pc_wb1; + logic [31:1] dec_i1_pc_wb1; logic dec_tlu_i1_valid_wb1, dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1; logic [4:0] dec_tlu_exc_cause_wb1; logic [31:0] dec_tlu_mtval_wb1; - logic dec_tlu_i0_exc_valid_wb1, dec_tlu_i1_exc_valid_wb1; + logic dec_tlu_i0_exc_valid_wb1, dec_tlu_i1_exc_valid_wb1; // also need retires_p==3 @@ -563,9 +563,9 @@ module dec assign trace_rv_trace_pkt.trace_rv_i_address_ip = { 32'b0, dec_i1_pc_wb1[31:1], 1'b0, dec_i0_pc_wb1[31:1], 1'b0 }; assign trace_rv_trace_pkt.trace_rv_i_valid_ip = {dec_tlu_int_valid_wb1, // always int - dec_tlu_i1_valid_wb1 | dec_tlu_i1_exc_valid_wb1, // not interrupts - dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1 - }; + dec_tlu_i1_valid_wb1 | dec_tlu_i1_exc_valid_wb1, // not interrupts + dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1 + }; assign trace_rv_trace_pkt.trace_rv_i_exception_ip = {dec_tlu_int_valid_wb1, dec_tlu_i1_exc_valid_wb1, dec_tlu_i0_exc_valid_wb1}; assign trace_rv_trace_pkt.trace_rv_i_ecause_ip = dec_tlu_exc_cause_wb1[4:0]; // replicate across ports assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = {dec_tlu_int_valid_wb1,2'b0}; diff --git a/design/dec/dec_decode_ctl.sv b/design/dec/dec_decode_ctl.sv index f5126b3..3e7d5ee 100644 --- a/design/dec/dec_decode_ctl.sv +++ b/design/dec/dec_decode_ctl.sv @@ -27,12 +27,12 @@ module dec_decode_ctl output logic [31:1] dec_i1_pc_wb1, - input logic lsu_nonblock_load_valid_dc3, // valid nonblock load at dc3 - input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // -> corresponding tag - input logic lsu_nonblock_load_inv_dc5, // invalidate request for nonblock load dc5 - input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // -> corresponding tag - input logic lsu_nonblock_load_data_valid, // valid nonblock load data back - input logic lsu_nonblock_load_data_error, // nonblock load bus error + input logic lsu_nonblock_load_valid_dc3, // valid nonblock load at dc3 + input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // -> corresponding tag + input logic lsu_nonblock_load_inv_dc5, // invalidate request for nonblock load dc5 + input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // -> corresponding tag + input logic lsu_nonblock_load_data_valid, // valid nonblock load data back + input logic lsu_nonblock_load_data_error, // nonblock load bus error input logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag input logic [3:0] dec_i0_trigger_match_d, // i0 decode trigger matches @@ -54,13 +54,13 @@ module dec_decode_ctl input logic [1:0] dbg_cmd_wrdata, // disambiguate fence, fence_i - input logic dec_i0_icaf_d, // icache access fault - input logic dec_i1_icaf_d, + input logic dec_i0_icaf_d, // icache access fault + input logic dec_i1_icaf_d, input logic dec_i0_icaf_f1_d, // i0 instruction access fault at decode for f1 fetch group - input logic dec_i0_perr_d, // icache parity error - input logic dec_i1_perr_d, + input logic dec_i0_perr_d, // icache parity error + input logic dec_i1_perr_d, input logic dec_i0_sbecc_d, // icache/iccm single-bit error - input logic dec_i1_sbecc_d, + input logic dec_i1_sbecc_d, input logic dec_i0_dbecc_d, // icache/iccm double-bit error input logic dec_i1_dbecc_d, @@ -87,7 +87,7 @@ module dec_decode_ctl input logic dec_tlu_flush_lower_wb, // trap lower flush input logic dec_tlu_flush_pause_wb, // don't clear pause state on initial lower flush - input logic dec_tlu_presync_d, // CSR read needs to be presync'd + input logic dec_tlu_presync_d, // CSR read needs to be presync'd input logic dec_tlu_postsync_d, // CSR ops that need to be postsync'd input logic [31:0] exu_mul_result_e3, // multiply result @@ -112,8 +112,8 @@ module dec_decode_ctl input logic [31:0] dec_i0_instr_d, // inst at decode input logic [31:0] dec_i1_instr_d, - input logic dec_ib0_valid_d, // inst valid at decode - input logic dec_ib1_valid_d, + input logic dec_ib0_valid_d, // inst valid at decode + input logic dec_ib1_valid_d, input logic [31:0] exu_i0_result_e1, // from primary alu's input logic [31:0] exu_i1_result_e1, @@ -121,16 +121,16 @@ module dec_decode_ctl input logic [31:0] exu_i0_result_e4, // from secondary alu's input logic [31:0] exu_i1_result_e4, - input logic clk, // for rvdffe's + input logic clk, // for rvdffe's input logic active_clk, // clk except for halt / pause input logic free_clk, // free running clock input logic clk_override, // test stuff - input logic rst_l, + input logic rst_l, - output logic dec_i0_rs1_en_d, // rs1 enable at decode - output logic dec_i0_rs2_en_d, + output logic dec_i0_rs1_en_d, // rs1 enable at decode + output logic dec_i0_rs2_en_d, output logic [4:0] dec_i0_rs1_d, // rs1 logical source output logic [4:0] dec_i0_rs2_d, @@ -139,8 +139,8 @@ module dec_decode_ctl output logic [31:0] dec_i0_immed_d, // 32b immediate data decode - output logic dec_i1_rs1_en_d, - output logic dec_i1_rs2_en_d, + output logic dec_i1_rs1_en_d, + output logic dec_i1_rs2_en_d, output logic [4:0] dec_i1_rs1_d, output logic [4:0] dec_i1_rs2_d, @@ -155,14 +155,14 @@ module dec_decode_ctl output alu_pkt_t i0_ap, // alu packets output alu_pkt_t i1_ap, - output logic dec_i0_decode_d, // i0 decode - output logic dec_i1_decode_d, + output logic dec_i0_decode_d, // i0 decode + output logic dec_i1_decode_d, output logic dec_ib0_valid_eff_d, // effective valid taking decode into account output logic dec_ib1_valid_eff_d, - output logic dec_i0_alu_decode_d, // decode to primary alu's - output logic dec_i1_alu_decode_d, + output logic dec_i0_alu_decode_d, // decode to primary alu's + output logic dec_i1_alu_decode_d, output logic [31:0] i0_rs1_bypass_data_d, // i0 rs1 bypass data @@ -172,15 +172,15 @@ module dec_decode_ctl output logic [4:0] dec_i0_waddr_wb, // i0 logical source to write to gpr's - output logic dec_i0_wen_wb, // i0 write enable + output logic dec_i0_wen_wb, // i0 write enable output logic [31:0] dec_i0_wdata_wb, // i0 write data output logic [4:0] dec_i1_waddr_wb, - output logic dec_i1_wen_wb, + output logic dec_i1_wen_wb, output logic [31:0] dec_i1_wdata_wb, - output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches - output logic dec_i1_select_pc_d, + output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches + output logic dec_i1_select_pc_d, output logic dec_i0_rs1_bypass_en_d, // i0 rs1 bypass enable output logic dec_i0_rs2_bypass_en_d, // i0 rs2 bypass enable @@ -214,10 +214,10 @@ module dec_decode_ctl output logic [31:0] dec_csr_wrdata_wb, // csr write data at wb output logic dec_csr_stall_int_ff, // csr is mie/mstatus - output dec_tlu_i0_valid_e4, // i0 valid inst at e4 - output dec_tlu_i1_valid_e4, - - output trap_pkt_t dec_tlu_packet_e4, // trap packet + output dec_tlu_i0_valid_e4, // i0 valid inst at e4 + output dec_tlu_i1_valid_e4, + + output trap_pkt_t dec_tlu_packet_e4, // trap packet output logic dec_fence_pending, // tell TLU to stall DMA output logic [31:1] dec_tlu_i0_pc_e4, // i0 trap pc @@ -288,7 +288,7 @@ module dec_decode_ctl logic [31:0] i0, i1; - logic i0_valid_d, i1_valid_d; + logic i0_valid_d, i1_valid_d; logic [31:0] i0_result_e1, i1_result_e1; logic [31:0] i1_result_e2; @@ -301,131 +301,131 @@ module dec_decode_ctl logic [31:1] i0_pc_e3, i1_pc_e3; logic [31:1] i0_pc_e4, i1_pc_e4; - logic [9:0] i0_rs1bypass, i0_rs2bypass; - logic [9:0] i1_rs1bypass, i1_rs2bypass; + logic [9:0] i0_rs1bypass, i0_rs2bypass; + logic [9:0] i1_rs1bypass, i1_rs2bypass; - logic i0_jalimm20, i1_jalimm20; - logic i0_uiimm20, i1_uiimm20; + logic i0_jalimm20, i1_jalimm20; + logic i0_uiimm20, i1_uiimm20; - //logic flush_final_e3; + //logic flush_final_e3; - logic lsu_decode_d; + logic lsu_decode_d; logic [31:0] i0_immed_d; - logic i0_presync; - logic i0_postsync; + logic i0_presync; + logic i0_postsync; - logic postsync_stall; - logic ps_stall; + logic postsync_stall; + logic ps_stall; - logic prior_inflight, prior_inflight_e1e4, prior_inflight_wb; + logic prior_inflight, prior_inflight_e1e4, prior_inflight_wb; - logic csr_clr_d, csr_set_d, csr_write_d; + logic csr_clr_d, csr_set_d, csr_write_d; - logic csr_clr_e1,csr_set_e1,csr_write_e1,csr_imm_e1; + logic csr_clr_e1,csr_set_e1,csr_write_e1,csr_imm_e1; logic [31:0] csr_mask_e1; logic [31:0] write_csr_data_e1; logic [31:0] write_csr_data_in; logic [31:0] write_csr_data; - logic csr_data_wen; + logic csr_data_wen; - logic [4:0] csrimm_e1; + logic [4:0] csrimm_e1; logic [31:0] csr_rddata_e1; - logic flush_lower_wb; + logic flush_lower_wb; - logic i1_load_block_d; - logic i1_mul_block_d; - logic i1_load2_block_d; - logic i1_mul2_block_d; - logic mul_decode_d; - logic div_decode_d; + logic i1_load_block_d; + logic i1_mul_block_d; + logic i1_load2_block_d; + logic i1_mul2_block_d; + logic mul_decode_d; + logic div_decode_d; logic [31:1] div_pc; - logic div_stall, div_stall_ff; - logic [3:0] div_trigger; + logic div_stall, div_stall_ff; + logic [3:0] div_trigger; - logic i0_legal; - logic shift_illegal; - logic illegal_inst_en; + logic i0_legal; + logic shift_illegal; + logic illegal_inst_en; logic [31:0] illegal_inst; - logic illegal_lockout_in, illegal_lockout; - logic i0_legal_decode_d; + logic illegal_lockout_in, illegal_lockout; + logic i0_legal_decode_d; - logic i1_flush_final_e3; + logic i1_flush_final_e3; logic [31:0] i0_result_e3_final, i1_result_e3_final; logic [31:0] i0_result_wb_raw, i1_result_wb_raw; - logic [12:1] last_br_immed_d; - logic i1_depend_i0_d; - logic i0_rs1_depend_i0_e1, i0_rs1_depend_i0_e2, i0_rs1_depend_i0_e3, i0_rs1_depend_i0_e4, i0_rs1_depend_i0_wb; - logic i0_rs1_depend_i1_e1, i0_rs1_depend_i1_e2, i0_rs1_depend_i1_e3, i0_rs1_depend_i1_e4, i0_rs1_depend_i1_wb; - logic i0_rs2_depend_i0_e1, i0_rs2_depend_i0_e2, i0_rs2_depend_i0_e3, i0_rs2_depend_i0_e4, i0_rs2_depend_i0_wb; - logic i0_rs2_depend_i1_e1, i0_rs2_depend_i1_e2, i0_rs2_depend_i1_e3, i0_rs2_depend_i1_e4, i0_rs2_depend_i1_wb; - logic i1_rs1_depend_i0_e1, i1_rs1_depend_i0_e2, i1_rs1_depend_i0_e3, i1_rs1_depend_i0_e4, i1_rs1_depend_i0_wb; - logic i1_rs1_depend_i1_e1, i1_rs1_depend_i1_e2, i1_rs1_depend_i1_e3, i1_rs1_depend_i1_e4, i1_rs1_depend_i1_wb; - logic i1_rs2_depend_i0_e1, i1_rs2_depend_i0_e2, i1_rs2_depend_i0_e3, i1_rs2_depend_i0_e4, i1_rs2_depend_i0_wb; - logic i1_rs2_depend_i1_e1, i1_rs2_depend_i1_e2, i1_rs2_depend_i1_e3, i1_rs2_depend_i1_e4, i1_rs2_depend_i1_wb; - logic i1_rs1_depend_i0_d, i1_rs2_depend_i0_d; + logic [12:1] last_br_immed_d; + logic i1_depend_i0_d; + logic i0_rs1_depend_i0_e1, i0_rs1_depend_i0_e2, i0_rs1_depend_i0_e3, i0_rs1_depend_i0_e4, i0_rs1_depend_i0_wb; + logic i0_rs1_depend_i1_e1, i0_rs1_depend_i1_e2, i0_rs1_depend_i1_e3, i0_rs1_depend_i1_e4, i0_rs1_depend_i1_wb; + logic i0_rs2_depend_i0_e1, i0_rs2_depend_i0_e2, i0_rs2_depend_i0_e3, i0_rs2_depend_i0_e4, i0_rs2_depend_i0_wb; + logic i0_rs2_depend_i1_e1, i0_rs2_depend_i1_e2, i0_rs2_depend_i1_e3, i0_rs2_depend_i1_e4, i0_rs2_depend_i1_wb; + logic i1_rs1_depend_i0_e1, i1_rs1_depend_i0_e2, i1_rs1_depend_i0_e3, i1_rs1_depend_i0_e4, i1_rs1_depend_i0_wb; + logic i1_rs1_depend_i1_e1, i1_rs1_depend_i1_e2, i1_rs1_depend_i1_e3, i1_rs1_depend_i1_e4, i1_rs1_depend_i1_wb; + logic i1_rs2_depend_i0_e1, i1_rs2_depend_i0_e2, i1_rs2_depend_i0_e3, i1_rs2_depend_i0_e4, i1_rs2_depend_i0_wb; + logic i1_rs2_depend_i1_e1, i1_rs2_depend_i1_e2, i1_rs2_depend_i1_e3, i1_rs2_depend_i1_e4, i1_rs2_depend_i1_wb; + logic i1_rs1_depend_i0_d, i1_rs2_depend_i0_d; - logic i0_secondary_d, i1_secondary_d; - logic i0_secondary_block_d, i1_secondary_block_d; - logic non_block_case_d; - logic i0_div_decode_d; + logic i0_secondary_d, i1_secondary_d; + logic i0_secondary_block_d, i1_secondary_block_d; + logic non_block_case_d; + logic i0_div_decode_d; logic [31:0] i0_result_e4_final, i1_result_e4_final; - logic i0_load_block_d; - logic i0_mul_block_d; - logic [3:0] i0_rs1_depth_d, i0_rs2_depth_d; - logic [3:0] i1_rs1_depth_d, i1_rs2_depth_d; + logic i0_load_block_d; + logic i0_mul_block_d; + logic [3:0] i0_rs1_depth_d, i0_rs2_depth_d; + logic [3:0] i1_rs1_depth_d, i1_rs2_depth_d; - logic i0_rs1_match_e1_e2, i0_rs1_match_e1_e3; - logic i0_rs2_match_e1_e2, i0_rs2_match_e1_e3; - logic i1_rs1_match_e1_e2, i1_rs1_match_e1_e3; - logic i1_rs2_match_e1_e2, i1_rs2_match_e1_e3; + logic i0_rs1_match_e1_e2, i0_rs1_match_e1_e3; + logic i0_rs2_match_e1_e2, i0_rs2_match_e1_e3; + logic i1_rs1_match_e1_e2, i1_rs1_match_e1_e3; + logic i1_rs2_match_e1_e2, i1_rs2_match_e1_e3; logic i0_load_stall_d, i1_load_stall_d; logic i0_store_stall_d, i1_store_stall_d; - logic i0_predict_nt, i0_predict_t; - logic i1_predict_nt, i1_predict_t; + logic i0_predict_nt, i0_predict_t; + logic i1_predict_nt, i1_predict_t; - logic i0_notbr_error, i0_br_toffset_error; - logic i1_notbr_error, i1_br_toffset_error; + logic i0_notbr_error, i0_br_toffset_error; + logic i1_notbr_error, i1_br_toffset_error; logic i0_ret_error, i1_ret_error; logic i0_br_error, i1_br_error; logic i0_br_error_all, i1_br_error_all; logic [11:0] i0_br_offset, i1_br_offset; - logic freeze; + logic freeze; logic [20:1] i0_pcall_imm, i1_pcall_imm; // predicted jal's - logic i0_pcall_12b_offset, i1_pcall_12b_offset; - logic i0_pcall_raw, i1_pcall_raw; - logic i0_pcall_case, i1_pcall_case; - logic i0_pcall, i1_pcall; + logic i0_pcall_12b_offset, i1_pcall_12b_offset; + logic i0_pcall_raw, i1_pcall_raw; + logic i0_pcall_case, i1_pcall_case; + logic i0_pcall, i1_pcall; - logic i0_pja_raw, i1_pja_raw; - logic i0_pja_case, i1_pja_case; - logic i0_pja, i1_pja; + logic i0_pja_raw, i1_pja_raw; + logic i0_pja_case, i1_pja_case; + logic i0_pja, i1_pja; - logic i0_pret_case, i1_pret_case; - logic i0_pret_raw, i0_pret; - logic i1_pret_raw, i1_pret; + logic i0_pret_case, i1_pret_case; + logic i0_pret_raw, i0_pret; + logic i1_pret_raw, i1_pret; - logic i0_jal, i1_jal; // jal's that are not predicted + logic i0_jal, i1_jal; // jal's that are not predicted - logic i0_predict_br, i1_predict_br; + logic i0_predict_br, i1_predict_br; - logic freeze_prior1, freeze_prior2; + logic freeze_prior1, freeze_prior2; logic [31:0] i0_result_e4_freeze, i1_result_e4_freeze; logic [31:0] i0_result_wb_freeze, i1_result_wb_freeze; logic [31:0] i1_result_wb_eff, i0_result_wb_eff; - logic [2:0] i1rs1_intra, i1rs2_intra; - logic i1_rs1_intra_bypass, i1_rs2_intra_bypass; - logic store_data_bypass_c1, store_data_bypass_c2; - logic [1:0] store_data_bypass_e4_c1, store_data_bypass_e4_c2, store_data_bypass_e4_c3; + logic [2:0] i1rs1_intra, i1rs2_intra; + logic i1_rs1_intra_bypass, i1_rs2_intra_bypass; + logic store_data_bypass_c1, store_data_bypass_c2; + logic [1:0] store_data_bypass_e4_c1, store_data_bypass_e4_c2, store_data_bypass_e4_c3; logic store_data_bypass_i0_e2_c2; class_pkt_t i0_rs1_class_d, i0_rs2_class_d; @@ -446,25 +446,25 @@ module dec_decode_ctl logic i1_ap_pc2, i1_ap_pc4; logic div_wen_wb; - logic i0_rd_en_d; - logic i1_rd_en_d; - logic [4:0] i1_rd_d; - logic [4:0] i0_rd_d; + logic i0_rd_en_d; + logic i1_rd_en_d; + logic [4:0] i1_rd_d; + logic [4:0] i0_rd_d; - logic load_ldst_bypass_c1; - logic load_mul_rs1_bypass_e1; - logic load_mul_rs2_bypass_e1; + logic load_ldst_bypass_c1; + logic load_mul_rs1_bypass_e1; + logic load_mul_rs2_bypass_e1; - logic leak1_i0_stall_in, leak1_i0_stall; - logic leak1_i1_stall_in, leak1_i1_stall; - logic leak1_mode; + logic leak1_i0_stall_in, leak1_i0_stall; + logic leak1_i1_stall_in, leak1_i1_stall; + logic leak1_mode; - logic i0_csr_write_only_d; + logic i0_csr_write_only_d; - logic prior_inflight_e1e3, prior_inflight_eff; - logic any_csr_d; + logic prior_inflight_e1e3, prior_inflight_eff; + logic any_csr_d; - logic prior_csr_write; + logic prior_csr_write; logic [5:0] i0_pipe_en; logic i0_e1_ctl_en, i0_e2_ctl_en, i0_e3_ctl_en, i0_e4_ctl_en, i0_wb_ctl_en; @@ -494,20 +494,20 @@ module dec_decode_ctl logic [31:1] i1_pc_wb; - logic i0_brp_valid; - logic nonblock_load_cancel; - logic lsu_idle; - logic csr_read_e1; - logic i0_block_d; - logic i1_block_d; - logic ps_stall_in; + logic i0_brp_valid; + logic nonblock_load_cancel; + logic lsu_idle; + logic csr_read_e1; + logic i0_block_d; + logic i1_block_d; + logic ps_stall_in; - logic freeze_after_unfreeze1; - logic freeze_after_unfreeze2; - logic unfreeze_cycle1; - logic unfreeze_cycle2; + logic freeze_after_unfreeze1; + logic freeze_after_unfreeze2; + logic unfreeze_cycle1; + logic unfreeze_cycle2; - logic tlu_wr_pause_wb1, tlu_wr_pause_wb2; + logic tlu_wr_pause_wb1, tlu_wr_pause_wb2; assign freeze = lsu_freeze_dc3; @@ -594,24 +594,24 @@ module dec_decode_ctl always_comb begin i0_dp = i0_dp_raw; if (i0_br_error_all | i0_instr_error) begin - i0_dp = '0; - i0_dp.alu = 1'b1; - i0_dp.rs1 = 1'b1; - i0_dp.rs2 = 1'b1; - i0_dp.lor = 1'b1; - i0_dp.legal = 1'b1; - i0_dp.postsync = 1'b1; + i0_dp = '0; + i0_dp.alu = 1'b1; + i0_dp.rs1 = 1'b1; + i0_dp.rs2 = 1'b1; + i0_dp.lor = 1'b1; + i0_dp.legal = 1'b1; + i0_dp.postsync = 1'b1; end i1_dp = i1_dp_raw; if (i1_br_error_all) begin - i1_dp = '0; - i1_dp.alu = 1'b1; - i1_dp.rs1 = 1'b1; - i1_dp.rs2 = 1'b1; - i1_dp.lor = 1'b1; - i1_dp.legal = 1'b1; - i1_dp.postsync = 1'b1; + i1_dp = '0; + i1_dp.alu = 1'b1; + i1_dp.rs1 = 1'b1; + i1_dp.rs2 = 1'b1; + i1_dp.lor = 1'b1; + i1_dp.legal = 1'b1; + i1_dp.postsync = 1'b1; end end @@ -700,7 +700,7 @@ module dec_decode_ctl // non block load cam logic - logic cam_write, cam_inv_reset, cam_data_reset; + logic cam_write, cam_inv_reset, cam_data_reset; logic [NBLOAD_TAG_MSB:0] cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag; logic [NBLOAD_SIZE_MSB:0] cam_wen; @@ -728,18 +728,18 @@ module dec_decode_ctl cam_wen[NBLOAD_SIZE_MSB:0] = '0; for (int i=0; i= 4'h4}} & {`RV_BHT_GHR_PAD, final_h }) | // 000H - ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h3}} & {`RV_BHT_GHR_PAD2, final_h}) | // P00H -`ifdef RV_BHT_GHR_SIZE_2 - ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h2}} & { 1'b0, final_h}) | // PP0H + ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h3}} & {`RV_BHT_GHR_PAD2, final_h}) | // P00H +`ifdef RV_BHT_GHR_SIZE_2 + ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h2}} & { 1'b0, final_h}) | // PP0H `else - ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h2}} & {fghr[`RV_BHT_GHR_SIZE-3:0], 1'b0, final_h}) | // PP0H + ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h2}} & {fghr[`RV_BHT_GHR_SIZE-3:0], 1'b0, final_h}) | // PP0H `endif - ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h1}} & {fghr[`RV_BHT_GHR_SIZE-2:0], final_h}) | // PPPH - ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h0}} & {fghr[`RV_BHT_GHR_RANGE]}) ); // PPPP + ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h1}} & {fghr[`RV_BHT_GHR_SIZE-2:0], final_h}) | // PPPH + ({`RV_BHT_GHR_SIZE{num_valids[3:0] == 4'h0}} & {fghr[`RV_BHT_GHR_RANGE]}) ); // PPPP logic [`RV_BHT_GHR_RANGE] exu_flush_ghr; assign exu_flush_ghr[`RV_BHT_GHR_RANGE] = exu_mp_fghr[`RV_BHT_GHR_RANGE]; assign fghr_ns[`RV_BHT_GHR_RANGE] = ( ({`RV_BHT_GHR_SIZE{exu_flush_final}} & exu_flush_ghr[`RV_BHT_GHR_RANGE]) | - ({`RV_BHT_GHR_SIZE{~exu_flush_final & ifc_fetch_req_f2_raw & ~leak_one_f2}} & merged_ghr[`RV_BHT_GHR_RANGE]) | - ({`RV_BHT_GHR_SIZE{~exu_flush_final & ~(ifc_fetch_req_f2_raw & ~leak_one_f2)}} & fghr[`RV_BHT_GHR_RANGE])); + ({`RV_BHT_GHR_SIZE{~exu_flush_final & ifc_fetch_req_f2_raw & ~leak_one_f2}} & merged_ghr[`RV_BHT_GHR_RANGE]) | + ({`RV_BHT_GHR_SIZE{~exu_flush_final & ~(ifc_fetch_req_f2_raw & ~leak_one_f2)}} & fghr[`RV_BHT_GHR_RANGE])); rvdff #(`RV_BHT_GHR_SIZE) fetchghr (.*, .clk(active_clk), .din(fghr_ns[`RV_BHT_GHR_RANGE]), .dout(fghr[`RV_BHT_GHR_RANGE])); assign ifu_bp_fghr_f2[`RV_BHT_GHR_RANGE] = fghr[`RV_BHT_GHR_RANGE]; @@ -1052,13 +1052,13 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] `ifdef RV_BTB_48 assign ifu_bp_way_f2 = {fetch_replway_bank7_enc[1:0], - fetch_replway_bank6_enc[1:0], - fetch_replway_bank5_enc[1:0], - fetch_replway_bank4_enc[1:0], - fetch_replway_bank3_enc[1:0], - fetch_replway_bank2_enc[1:0], - fetch_replway_bank1_enc[1:0], - fetch_replway_bank0_enc[1:0]}; + fetch_replway_bank6_enc[1:0], + fetch_replway_bank5_enc[1:0], + fetch_replway_bank4_enc[1:0], + fetch_replway_bank3_enc[1:0], + fetch_replway_bank2_enc[1:0], + fetch_replway_bank1_enc[1:0], + fetch_replway_bank0_enc[1:0]}; `else assign ifu_bp_way_f2[7:0] = way_raw[7:0]; @@ -1073,42 +1073,42 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] // Truncate taken and valid, used for detecting a taken branch in the fetch group always_comb begin casez(ifc_fetch_addr_f2[3:1]) - 3'b000 : begin - bp_hist1_f2[7:0] = hist1_raw[7:0]; - bp_valid_f2[7:0] = wayhit_f2[7:0]; - end - 3'b001 : begin - bp_hist1_f2[7:0] = {1'b0, hist1_raw[7:1]}; - bp_valid_f2[7:0] = {1'b0, wayhit_f2[7:1]}; - end - 3'b010 : begin - bp_hist1_f2[7:0] = {2'b0, hist1_raw[7:2]}; - bp_valid_f2[7:0] = {2'b0, wayhit_f2[7:2]}; - end - 3'b011 : begin - bp_hist1_f2[7:0] = {3'b0, hist1_raw[7:3]}; - bp_valid_f2[7:0] = {3'b0, wayhit_f2[7:3]}; - end - 3'b100 : begin - bp_hist1_f2[7:0] = {4'b0, hist1_raw[7:4]}; - bp_valid_f2[7:0] = {4'b0, wayhit_f2[7:4]}; - end - 3'b101 : begin - bp_hist1_f2[7:0] = {5'b0, hist1_raw[7:5]}; - bp_valid_f2[7:0] = {5'b0, wayhit_f2[7:5]}; - end - 3'b110 : begin - bp_hist1_f2[7:0] = {6'b0, hist1_raw[7:6]}; - bp_valid_f2[7:0] = {6'b0, wayhit_f2[7:6]}; - end - 3'b111 : begin - bp_hist1_f2[7:0] = {7'b0, hist1_raw[7]}; - bp_valid_f2[7:0] = {7'b0, wayhit_f2[7]}; - end + 3'b000 : begin + bp_hist1_f2[7:0] = hist1_raw[7:0]; + bp_valid_f2[7:0] = wayhit_f2[7:0]; + end + 3'b001 : begin + bp_hist1_f2[7:0] = {1'b0, hist1_raw[7:1]}; + bp_valid_f2[7:0] = {1'b0, wayhit_f2[7:1]}; + end + 3'b010 : begin + bp_hist1_f2[7:0] = {2'b0, hist1_raw[7:2]}; + bp_valid_f2[7:0] = {2'b0, wayhit_f2[7:2]}; + end + 3'b011 : begin + bp_hist1_f2[7:0] = {3'b0, hist1_raw[7:3]}; + bp_valid_f2[7:0] = {3'b0, wayhit_f2[7:3]}; + end + 3'b100 : begin + bp_hist1_f2[7:0] = {4'b0, hist1_raw[7:4]}; + bp_valid_f2[7:0] = {4'b0, wayhit_f2[7:4]}; + end + 3'b101 : begin + bp_hist1_f2[7:0] = {5'b0, hist1_raw[7:5]}; + bp_valid_f2[7:0] = {5'b0, wayhit_f2[7:5]}; + end + 3'b110 : begin + bp_hist1_f2[7:0] = {6'b0, hist1_raw[7:6]}; + bp_valid_f2[7:0] = {6'b0, wayhit_f2[7:6]}; + end + 3'b111 : begin + bp_hist1_f2[7:0] = {7'b0, hist1_raw[7]}; + bp_valid_f2[7:0] = {7'b0, wayhit_f2[7]}; + end default: begin - bp_hist1_f2[7:0] = hist1_raw[7:0]; - bp_valid_f2[7:0] = wayhit_f2[7:0]; - end + bp_hist1_f2[7:0] = hist1_raw[7:0]; + bp_valid_f2[7:0] = wayhit_f2[7:0]; + end endcase // casex (ifc_fetch_addr_f1[3:2]) end @@ -1121,8 +1121,8 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] assign btb_sel_f2_enc_shift[2:0] = encode8_3({1'b0,btb_sel_f2[7:1]}); assign bp_total_branch_offset_f2[3:1] = (({3{ btb_rd_pc4_f2}} & btb_sel_f2_enc_shift[2:0]) | - ({3{~btb_rd_pc4_f2}} & btb_sel_f2_enc[2:0]) | - ({3{btb_fg_crossing_f2}})); + ({3{~btb_rd_pc4_f2}} & btb_sel_f2_enc[2:0]) | + ({3{btb_fg_crossing_f2}})); logic [31:4] adder_pc_in_f2, ifc_fetch_adder_prior; @@ -1131,12 +1131,12 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] assign ifu_bp_poffset_f2[11:0] = btb_rd_tgt_f2[11:0]; assign adder_pc_in_f2[31:4] = ( ({28{ btb_fg_crossing_f2}} & ifc_fetch_adder_prior[31:4]) | - ({28{~btb_fg_crossing_f2}} & ifc_fetch_addr_f2[31:4])); + ({28{~btb_fg_crossing_f2}} & ifc_fetch_addr_f2[31:4])); rvbradder predtgt_addr (.pc({adder_pc_in_f2[31:4], bp_total_branch_offset_f2[3:1]}), - .offset(btb_rd_tgt_f2[11:0]), - .dout(bp_btb_target_adder_f2[31:1]) - ); + .offset(btb_rd_tgt_f2[11:0]), + .dout(bp_btb_target_adder_f2[31:1]) + ); // mux in the return stack address here for a predicted return assign ifu_bp_btb_target_f2[31:1] = btb_rd_ret_f2 & ~btb_rd_call_f2 ? rets_out[0][31:1] : bp_btb_target_adder_f2[31:1]; @@ -1146,9 +1146,9 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] // ---------------------------------------------------------------------- rvbradder rs_addr (.pc({adder_pc_in_f2[31:4], bp_total_branch_offset_f2[3:1]}), - .offset({10'b0, btb_rd_pc4_f2, ~btb_rd_pc4_f2}), - .dout(bp_rs_call_target_f2[31:1]) - ); + .offset({10'b0, btb_rd_pc4_f2, ~btb_rd_pc4_f2}), + .dout(bp_rs_call_target_f2[31:1]) + ); // Calls/Rets are always taken, so there shouldn't be a push and pop in the same fetch group logic rs_overpop_correct, rsoverpop_valid_ns, rsoverpop_valid_f; @@ -1161,7 +1161,7 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] assign rsunderpop_valid_ns = (rs_push | (rsunderpop_valid_f & ~(exu_i0_br_call_e4 | exu_i1_br_call_e4))) & ~exu_flush_final; assign rsoverpop_valid_ns = (rs_pop | (rsoverpop_valid_f & ~(exu_i0_br_ret_e4 | exu_i1_br_ret_e4))) & ~exu_flush_final; assign rsoverpop_ns[31:1] = ( ({31{rs_pop}} & rets_out[0][31:1]) | - ({31{~rs_pop}} & rsoverpop_f[31:1]) ); + ({31{~rs_pop}} & rsoverpop_f[31:1]) ); rvdff #(33) retoverpop_ff (.*, .clk(active_clk), .din({rsunderpop_valid_ns, rsoverpop_valid_ns, rsoverpop_ns[31:1]}), .dout({rsunderpop_valid_f, rsoverpop_valid_f, rsoverpop_f[31:1]})); `else @@ -1186,13 +1186,13 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] // Fetch based assign rets_in[0][31:1] = ( ({31{rs_overpop_correct & rs_underpop_correct}} & rsoverpop_f[31:1]) | - ({31{rs_push & rs_overpop_correct}} & rsoverpop_f[31:1]) | - ({31{rs_push & ~rs_overpop_correct}} & bp_rs_call_target_f2[31:1]) | -`ifdef REAL_COMM_RS - ({31{rs_correct}} & e1_rets_out[0][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[0][31:1]) | -`endif - ({31{rs_pop}} & rets_out[1][31:1]) ); + ({31{rs_push & rs_overpop_correct}} & rsoverpop_f[31:1]) | + ({31{rs_push & ~rs_overpop_correct}} & bp_rs_call_target_f2[31:1]) | +`ifdef REAL_COMM_RS + ({31{rs_correct}} & e1_rets_out[0][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[0][31:1]) | +`endif + ({31{rs_pop}} & rets_out[1][31:1]) ); assign rsenable[0] = ~rs_hold; @@ -1200,26 +1200,26 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] // for the last entry in the stack, we don't have a pop position if(i==`RV_RET_STACK_SIZE-1) begin -`ifdef REAL_COMM_RS - assign rets_in[i][31:1] = ( ({31{rs_push}} & rets_out[i-1][31:1]) | - ({31{rs_correct}} & e1_rets_out[i][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) ); +`ifdef REAL_COMM_RS + assign rets_in[i][31:1] = ( ({31{rs_push}} & rets_out[i-1][31:1]) | + ({31{rs_correct}} & e1_rets_out[i][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) ); `else - assign rets_in[i][31:1] = rets_out[i-1][31:1]; -`endif - assign rsenable[i] = rs_push | rs_correct | e4_rs_correct; + assign rets_in[i][31:1] = rets_out[i-1][31:1]; +`endif + assign rsenable[i] = rs_push | rs_correct | e4_rs_correct; end else if(i>0) begin -`ifdef REAL_COMM_RS - assign rets_in[i][31:1] = ( ({31{rs_push}} & rets_out[i-1][31:1]) | - ({31{rs_pop}} & rets_out[i+1][31:1]) | - ({31{rs_correct}} & e1_rets_out[i][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) ); -`else - assign rets_in[i][31:1] = ( ({31{rs_push}} & rets_out[i-1][31:1]) | - ({31{rs_pop}} & rets_out[i+1][31:1]) ); -`endif - assign rsenable[i] = rs_push | rs_pop | rs_correct | e4_rs_correct; +`ifdef REAL_COMM_RS + assign rets_in[i][31:1] = ( ({31{rs_push}} & rets_out[i-1][31:1]) | + ({31{rs_pop}} & rets_out[i+1][31:1]) | + ({31{rs_correct}} & e1_rets_out[i][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) ); +`else + assign rets_in[i][31:1] = ( ({31{rs_push}} & rets_out[i-1][31:1]) | + ({31{rs_pop}} & rets_out[i+1][31:1]) ); +`endif + assign rsenable[i] = rs_push | rs_pop | rs_correct | e4_rs_correct; end rvdffe #(31) rets_ff (.*, .en(rsenable[i]), .din(rets_in[i][31:1]), .dout(rets_out[i][31:1])); @@ -1240,53 +1240,53 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] assign e1_rs_hold = (~e1_rs_push1 & ~e1_rs_push2 & ~e1_rs_pop1 & ~e1_rs_pop2 & ~e4_rs_correct); rvbradder e1_rs_addr0 (.pc({exu_i0_pc_e1[31:1]}), - .offset({10'b0, exu_rets_e1_pkt.pc0_pc4, ~exu_rets_e1_pkt.pc0_pc4}), - .dout(e1_rs_call0_target_f2[31:1]) - ); + .offset({10'b0, exu_rets_e1_pkt.pc0_pc4, ~exu_rets_e1_pkt.pc0_pc4}), + .dout(e1_rs_call0_target_f2[31:1]) + ); rvbradder e1_rs_addr1 (.pc({exu_i1_pc_e1[31:1]}), - .offset({10'b0, exu_rets_e1_pkt.pc1_pc4, ~exu_rets_e1_pkt.pc1_pc4}), - .dout(e1_rs_call1_target_f2[31:1]) - ); + .offset({10'b0, exu_rets_e1_pkt.pc1_pc4, ~exu_rets_e1_pkt.pc1_pc4}), + .dout(e1_rs_call1_target_f2[31:1]) + ); assign e1_rs_call_target_f2[31:1] = exu_rets_e1_pkt.pc0_call ? e1_rs_call0_target_f2[31:1] : e1_rs_call1_target_f2[31:1]; assign e1_rets_in[0][31:1] = ( ({31{e1_rs_push1}} & e1_rs_call_target_f2[31:1]) | - ({31{e1_rs_push2}} & e1_rs_call1_target_f2[31:1]) | - ({31{e1_rs_pop1}} & e1_rets_out[1][31:1]) | - ({31{e1_rs_pop2}} & e1_rets_out[2][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[0][31:1]) | - ({31{e1_rs_hold}} & e1_rets_out[0][31:1]) ); + ({31{e1_rs_push2}} & e1_rs_call1_target_f2[31:1]) | + ({31{e1_rs_pop1}} & e1_rets_out[1][31:1]) | + ({31{e1_rs_pop2}} & e1_rets_out[2][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[0][31:1]) | + ({31{e1_rs_hold}} & e1_rets_out[0][31:1]) ); assign e1_rets_in[1][31:1] = ( ({31{e1_rs_push1}} & e1_rets_out[0][31:1]) | - ({31{e1_rs_push2}} & e1_rs_call0_target_f2[31:1]) | - ({31{e1_rs_pop1}} & e1_rets_out[2][31:1]) | - ({31{e1_rs_pop2}} & e1_rets_out[3][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[1][31:1]) | - ({31{e1_rs_hold}} & e1_rets_out[0][31:1]) ); + ({31{e1_rs_push2}} & e1_rs_call0_target_f2[31:1]) | + ({31{e1_rs_pop1}} & e1_rets_out[2][31:1]) | + ({31{e1_rs_pop2}} & e1_rets_out[3][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[1][31:1]) | + ({31{e1_rs_hold}} & e1_rets_out[0][31:1]) ); for (i=0; i<`RV_RET_STACK_SIZE; i++) begin : e1_retstack // for the last entry in the stack, we don't have a pop position if(i==`RV_RET_STACK_SIZE-1) - assign e1_rets_in[i][31:1] = ( ({31{e1_rs_push1}} & e1_rets_out[i-1][31:1]) | - ({31{e1_rs_push2}} & e1_rets_out[i-2][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) | - ({31{e1_rs_hold}} & e1_rets_out[i][31:1]) ); + assign e1_rets_in[i][31:1] = ( ({31{e1_rs_push1}} & e1_rets_out[i-1][31:1]) | + ({31{e1_rs_push2}} & e1_rets_out[i-2][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) | + ({31{e1_rs_hold}} & e1_rets_out[i][31:1]) ); else if(i==`RV_RET_STACK_SIZE-2) - assign e1_rets_in[i][31:1] = ( ({31{e1_rs_push1}} & e1_rets_out[i-1][31:1]) | - ({31{e1_rs_push2}} & e1_rets_out[i-2][31:1]) | - ({31{e1_rs_pop1}} & e1_rets_out[i+1][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) | - ({31{e1_rs_hold}} & e1_rets_out[i][31:1]) ); + assign e1_rets_in[i][31:1] = ( ({31{e1_rs_push1}} & e1_rets_out[i-1][31:1]) | + ({31{e1_rs_push2}} & e1_rets_out[i-2][31:1]) | + ({31{e1_rs_pop1}} & e1_rets_out[i+1][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) | + ({31{e1_rs_hold}} & e1_rets_out[i][31:1]) ); else if(i>1) - assign e1_rets_in[i][31:1] = ( ({31{e1_rs_push1}} & e1_rets_out[i-1][31:1]) | - ({31{e1_rs_push2}} & e1_rets_out[i-2][31:1]) | - ({31{e1_rs_pop1}} & e1_rets_out[i+1][31:1]) | - ({31{e1_rs_pop2}} & e1_rets_out[i+2][31:1]) | - ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) | - ({31{e1_rs_hold}} & e1_rets_out[i][31:1]) ); + assign e1_rets_in[i][31:1] = ( ({31{e1_rs_push1}} & e1_rets_out[i-1][31:1]) | + ({31{e1_rs_push2}} & e1_rets_out[i-2][31:1]) | + ({31{e1_rs_pop1}} & e1_rets_out[i+1][31:1]) | + ({31{e1_rs_pop2}} & e1_rets_out[i+2][31:1]) | + ({31{e4_rs_correct}} & e4_rets_out[i][31:1]) | + ({31{e1_rs_hold}} & e1_rets_out[i][31:1]) ); rvdff #(31) e1_rets_ff (.*, .din(e1_rets_in[i][31:1]), .dout(e1_rets_out[i][31:1])); @@ -1302,48 +1302,48 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] assign e4_rs_hold = (~e4_rs_push1 & ~e4_rs_push2 & ~e4_rs_pop1 & ~e4_rs_pop2); rvbradder e4_rs_addr0 (.pc({dec_tlu_i0_pc_e4[31:1]}), - .offset({10'b0, exu_rets_e4_pkt.pc0_pc4, ~exu_rets_e4_pkt.pc0_pc4}), - .dout(e4_rs_call0_target_f2[31:1]) - ); + .offset({10'b0, exu_rets_e4_pkt.pc0_pc4, ~exu_rets_e4_pkt.pc0_pc4}), + .dout(e4_rs_call0_target_f2[31:1]) + ); rvbradder e4_rs_addr1 (.pc({dec_tlu_i1_pc_e4[31:1]}), - .offset({10'b0, exu_rets_e4_pkt.pc1_pc4, ~exu_rets_e4_pkt.pc1_pc4}), - .dout(e4_rs_call1_target_f2[31:1]) - ); + .offset({10'b0, exu_rets_e4_pkt.pc1_pc4, ~exu_rets_e4_pkt.pc1_pc4}), + .dout(e4_rs_call1_target_f2[31:1]) + ); assign e4_rs_call_target_f2[31:1] = exu_rets_e4_pkt.pc0_call ? e4_rs_call0_target_f2[31:1] : e4_rs_call1_target_f2[31:1]; assign e4_rets_in[0][31:1] = ( ({31{e4_rs_push1}} & e4_rs_call_target_f2[31:1]) | - ({31{e4_rs_push2}} & e4_rs_call1_target_f2[31:1]) | - ({31{e4_rs_pop1}} & e4_rets_out[1][31:1]) | - ({31{e4_rs_pop2}} & e4_rets_out[2][31:1]) | - ({31{e4_rs_hold}} & e4_rets_out[0][31:1]) ); + ({31{e4_rs_push2}} & e4_rs_call1_target_f2[31:1]) | + ({31{e4_rs_pop1}} & e4_rets_out[1][31:1]) | + ({31{e4_rs_pop2}} & e4_rets_out[2][31:1]) | + ({31{e4_rs_hold}} & e4_rets_out[0][31:1]) ); assign e4_rets_in[1][31:1] = ( ({31{e4_rs_push1}} & e4_rets_out[0][31:1]) | - ({31{e4_rs_push2}} & e4_rs_call0_target_f2[31:1]) | - ({31{e4_rs_pop1}} & e4_rets_out[2][31:1]) | - ({31{e4_rs_pop2}} & e4_rets_out[3][31:1]) | - ({31{e4_rs_hold}} & e4_rets_out[0][31:1]) ); + ({31{e4_rs_push2}} & e4_rs_call0_target_f2[31:1]) | + ({31{e4_rs_pop1}} & e4_rets_out[2][31:1]) | + ({31{e4_rs_pop2}} & e4_rets_out[3][31:1]) | + ({31{e4_rs_hold}} & e4_rets_out[0][31:1]) ); for (i=0; i<`RV_RET_STACK_SIZE; i++) begin : e4_retstack // for the last entry in the stack, we don't have a pop position if(i==`RV_RET_STACK_SIZE-1) - assign e4_rets_in[i][31:1] = ( ({31{e4_rs_push1}} & e4_rets_out[i-1][31:1]) | - ({31{e4_rs_push2}} & e4_rets_out[i-2][31:1]) | - ({31{e4_rs_hold}} & e4_rets_out[i][31:1]) ); + assign e4_rets_in[i][31:1] = ( ({31{e4_rs_push1}} & e4_rets_out[i-1][31:1]) | + ({31{e4_rs_push2}} & e4_rets_out[i-2][31:1]) | + ({31{e4_rs_hold}} & e4_rets_out[i][31:1]) ); else if(i==`RV_RET_STACK_SIZE-2) - assign e4_rets_in[i][31:1] = ( ({31{e4_rs_push1}} & e4_rets_out[i-1][31:1]) | - ({31{e4_rs_push2}} & e4_rets_out[i-2][31:1]) | - ({31{e4_rs_pop1}} & e4_rets_out[i+1][31:1]) | - ({31{e4_rs_hold}} & e4_rets_out[i][31:1]) ); + assign e4_rets_in[i][31:1] = ( ({31{e4_rs_push1}} & e4_rets_out[i-1][31:1]) | + ({31{e4_rs_push2}} & e4_rets_out[i-2][31:1]) | + ({31{e4_rs_pop1}} & e4_rets_out[i+1][31:1]) | + ({31{e4_rs_hold}} & e4_rets_out[i][31:1]) ); else if(i>1) - assign e4_rets_in[i][31:1] = ( ({31{e4_rs_push1}} & e4_rets_out[i-1][31:1]) | - ({31{e4_rs_push2}} & e4_rets_out[i-2][31:1]) | - ({31{e4_rs_pop1}} & e4_rets_out[i+1][31:1]) | - ({31{e4_rs_pop2}} & e4_rets_out[i+2][31:1]) | - ({31{e4_rs_hold}} & e4_rets_out[i][31:1]) ); + assign e4_rets_in[i][31:1] = ( ({31{e4_rs_push1}} & e4_rets_out[i-1][31:1]) | + ({31{e4_rs_push2}} & e4_rets_out[i-2][31:1]) | + ({31{e4_rs_pop1}} & e4_rets_out[i+1][31:1]) | + ({31{e4_rs_pop2}} & e4_rets_out[i+2][31:1]) | + ({31{e4_rs_hold}} & e4_rets_out[i][31:1]) ); rvdff #(31) e4_rets_ff (.*, .din(e4_rets_in[i][31:1]), .dout(e4_rets_out[i][31:1])); @@ -1376,31 +1376,31 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] assign btb_wr_data[16+`RV_BTB_BTAG_SIZE:0] = {btb_wr_tag[`RV_BTB_BTAG_SIZE-1:0], exu_mp_tgt[11:0], exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ; assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken; -`ifdef RV_BTB_48 +`ifdef RV_BTB_48 assign btb_wr_en_way0[3:0] = ( ({4{(exu_mp_way==2'b0) & exu_mp_valid_write & ~dec_tlu_error_wb}} & decode2_4(exu_mp_bank[1:0])) | - ({4{(dec_tlu_way_wb==2'b0) & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | - ({4{(dec_tlu_way_wb==2'b0) & dec_tlu_all_banks_error_wb}})); - + ({4{(dec_tlu_way_wb==2'b0) & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | + ({4{(dec_tlu_way_wb==2'b0) & dec_tlu_all_banks_error_wb}})); + assign btb_wr_en_way1[3:0] = ( ({4{exu_mp_way[0] & exu_mp_valid_write & ~dec_tlu_error_wb}} & decode2_4(exu_mp_bank[1:0])) | - ({4{dec_tlu_way_wb[0] & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | - ({4{dec_tlu_way_wb[0] & dec_tlu_all_banks_error_wb}})); + ({4{dec_tlu_way_wb[0] & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | + ({4{dec_tlu_way_wb[0] & dec_tlu_all_banks_error_wb}})); assign btb_wr_en_way2[3:0] = ( ({4{exu_mp_way[1] & exu_mp_valid_write & ~dec_tlu_error_wb}} & decode2_4(exu_mp_bank[1:0])) | - ({4{dec_tlu_way_wb[1] & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | - ({4{dec_tlu_way_wb[1] & dec_tlu_all_banks_error_wb}})); + ({4{dec_tlu_way_wb[1] & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | + ({4{dec_tlu_way_wb[1] & dec_tlu_all_banks_error_wb}})); `else // !`ifdef RV_BTB_48 assign btb_wr_en_way0[3:0] = ( ({4{~exu_mp_way & exu_mp_valid_write & ~dec_tlu_error_wb}} & decode2_4(exu_mp_bank[1:0])) | - ({4{~dec_tlu_way_wb & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | - ({4{~dec_tlu_way_wb & dec_tlu_all_banks_error_wb}})); - + ({4{~dec_tlu_way_wb & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | + ({4{~dec_tlu_way_wb & dec_tlu_all_banks_error_wb}})); + assign btb_wr_en_way1[3:0] = ( ({4{exu_mp_way & exu_mp_valid_write & ~dec_tlu_error_wb}} & decode2_4(exu_mp_bank[1:0])) | - ({4{dec_tlu_way_wb & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | - ({4{dec_tlu_way_wb & dec_tlu_all_banks_error_wb}})); + ({4{dec_tlu_way_wb & dec_tlu_error_wb & ~dec_tlu_all_banks_error_wb}} & decode2_4(dec_tlu_error_bank_wb[1:0])) | + ({4{dec_tlu_way_wb & dec_tlu_all_banks_error_wb}})); `endif - + assign btb_wr_addr[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] = dec_tlu_error_wb ? btb_error_addr_wb[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] : exu_mp_addr[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO]; logic [1:0] bht_wr_data0, bht_wr_data1, bht_wr_data2; @@ -1506,63 +1506,63 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] end rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank0_way0_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank0_rd_data_way0_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank0_rd_data_way0_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank1_way0_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank1_rd_data_way0_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank1_rd_data_way0_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank2_way0_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank2_rd_data_way0_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank2_rd_data_way0_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank3_way0_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank3_rd_data_way0_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank3_rd_data_way0_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank0_way1_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank0_rd_data_way1_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank0_rd_data_way1_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank1_way1_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank1_rd_data_way1_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank1_rd_data_way1_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank2_way1_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank2_rd_data_way1_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank2_rd_data_way1_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank3_way1_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank3_rd_data_way1_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank3_rd_data_way1_f2 [16+`RV_BTB_BTAG_SIZE:0])); `ifdef RV_BTB_48 rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank0_way2_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank0_rd_data_way2_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank0_rd_data_way2_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank1_way2_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank1_rd_data_way2_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank1_rd_data_way2_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank2_way2_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank2_rd_data_way2_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank2_rd_data_way2_f2 [16+`RV_BTB_BTAG_SIZE:0])); rvdffe #(17+`RV_BTB_BTAG_SIZE) btb_bank3_way2_data_out (.*, - .en(ifc_fetch_req_f1), + .en(ifc_fetch_req_f1), .din (btb_bank3_rd_data_way2_f2_in[16+`RV_BTB_BTAG_SIZE:0]), .dout (btb_bank3_rd_data_way2_f2 [16+`RV_BTB_BTAG_SIZE:0])); `endif // `ifdef RV_BTB_48 @@ -1603,7 +1603,7 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] btb_bank2_rd_data_way2_f2_in[16+`RV_BTB_BTAG_SIZE:0] = btb_bank2_rd_data_way2_out[j]; btb_bank3_rd_data_way2_f2_in[16+`RV_BTB_BTAG_SIZE:0] = btb_bank3_rd_data_way2_out[j]; `endif - + end end end @@ -1649,7 +1649,7 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] end // block: BHT_FLOPS end // block: BHT_CLK_GROUP end // block: BANKS - + always_comb begin : BHT_rd_mux bht_bank0_rd_data_f2_in[1:0] = '0 ; bht_bank1_rd_data_f2_in[1:0] = '0 ; @@ -1672,28 +1672,28 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] end end end // block: BHT_rd_mux - - + + rvdffe #(16) bht_dataoutf (.*, .en (ifc_fetch_req_f1), .din ({bht_bank0_rd_data_f2_in[1:0], - bht_bank1_rd_data_f2_in[1:0], - bht_bank2_rd_data_f2_in[1:0], - bht_bank3_rd_data_f2_in[1:0], - bht_bank4_rd_data_f2_in[1:0], - bht_bank5_rd_data_f2_in[1:0], - bht_bank6_rd_data_f2_in[1:0], - bht_bank7_rd_data_f2_in[1:0] - }), + bht_bank1_rd_data_f2_in[1:0], + bht_bank2_rd_data_f2_in[1:0], + bht_bank3_rd_data_f2_in[1:0], + bht_bank4_rd_data_f2_in[1:0], + bht_bank5_rd_data_f2_in[1:0], + bht_bank6_rd_data_f2_in[1:0], + bht_bank7_rd_data_f2_in[1:0] + }), .dout ({bht_bank0_rd_data_f2 [1:0], - bht_bank1_rd_data_f2 [1:0], - bht_bank2_rd_data_f2 [1:0], - bht_bank3_rd_data_f2 [1:0], - bht_bank4_rd_data_f2 [1:0], - bht_bank5_rd_data_f2 [1:0], - bht_bank6_rd_data_f2 [1:0], - bht_bank7_rd_data_f2 [1:0] - })); + bht_bank1_rd_data_f2 [1:0], + bht_bank2_rd_data_f2 [1:0], + bht_bank3_rd_data_f2 [1:0], + bht_bank4_rd_data_f2 [1:0], + bht_bank5_rd_data_f2 [1:0], + bht_bank6_rd_data_f2 [1:0], + bht_bank7_rd_data_f2 [1:0] + })); @@ -1705,7 +1705,7 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] encode8_3[1] = in[7] | in[6] | in[3] | in[2]; encode8_3[0] = in[7] | in[5] | in[3] | in[1]; - endfunction + endfunction function [7:0] decode3_8; input [2:0] in; @@ -1735,13 +1735,13 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2] begin countones[3:0] = {3'b0, valid[7]} + - {3'b0, valid[6]} + - {3'b0, valid[5]} + - {3'b0, valid[4]} + - {3'b0, valid[3]} + - {3'b0, valid[2]} + - {3'b0, valid[1]} + - {3'b0, valid[0]}; + {3'b0, valid[6]} + + {3'b0, valid[5]} + + {3'b0, valid[4]} + + {3'b0, valid[3]} + + {3'b0, valid[2]} + + {3'b0, valid[1]} + + {3'b0, valid[0]}; end endfunction function [2:0] newlru; // updated lru @@ -1765,10 +1765,10 @@ newlru[0] = (~lru[2] & lru[1] & ~used[1] & ~used[0]) | (~lru[1] & ~lru[0] & used input [2:0] v; // current way valids begin `ifdef BTB_ROUND_ROBIN - lru2way[1:0] = lru[1:0]; + lru2way[1:0] = lru[1:0]; `else - lru2way[1] = (~lru[2] & lru[1] & ~lru[0] & v[1] & v[0]) | (lru[2] & lru[0] & v[1] & v[0]) | (~v[2] & v[1] & v[0]); - lru2way[0] = (lru[2] & ~lru[0] & v[2] & v[0]) | (~v[1] & v[0]); + lru2way[1] = (~lru[2] & lru[1] & ~lru[0] & v[1] & v[0]) | (lru[2] & lru[0] & v[1] & v[0]) | (~v[2] & v[1] & v[0]); + lru2way[0] = (lru[2] & ~lru[0] & v[2] & v[0]) | (~v[1] & v[0]); `endif end endfunction diff --git a/design/ifu/ifu_compress_ctl.sv b/design/ifu/ifu_compress_ctl.sv index 250a0c8..de176a4 100644 --- a/design/ifu/ifu_compress_ctl.sv +++ b/design/ifu/ifu_compress_ctl.sv @@ -34,7 +34,7 @@ module ifu_compress_ctl assign i[15:0] = din[15:0]; - logic [4:0] rs2d,rdd,rdpd,rs2pd; + logic [4:0] rs2d,rdd,rdpd,rs2pd; logic rdrd; logic rdrs1; @@ -86,25 +86,25 @@ logic uswspimm7_2; assign l1[6:0] = o[6:0]; assign l1[11:7] = o[11:7] | - ({5{rdrd}} & rdd[4:0]) | - ({5{rdprd}} & rdpd[4:0]) | - ({5{rs2prd}} & rs2pd[4:0]) | - ({5{rdeq1}} & 5'd1) | - ({5{rdeq2}} & 5'd2); + ({5{rdrd}} & rdd[4:0]) | + ({5{rdprd}} & rdpd[4:0]) | + ({5{rs2prd}} & rs2pd[4:0]) | + ({5{rdeq1}} & 5'd1) | + ({5{rdeq2}} & 5'd2); - // rs1 + // rs1 assign l1[14:12] = o[14:12]; assign l1[19:15] = o[19:15] | - ({5{rdrs1}} & rdd[4:0]) | - ({5{rdprs1}} & rdpd[4:0]) | - ({5{rs1eq2}} & 5'd2); + ({5{rdrs1}} & rdd[4:0]) | + ({5{rdprs1}} & rdpd[4:0]) | + ({5{rs1eq2}} & 5'd2); // rs2 assign l1[24:20] = o[24:20] | - ({5{rs2rs2}} & rs2d[4:0]) | - ({5{rs2prs2}} & rs2pd[4:0]); + ({5{rs2rs2}} & rs2d[4:0]) | + ({5{rs2prs2}} & rs2pd[4:0]); assign l1[31:25] = o[31:25]; @@ -143,20 +143,20 @@ logic uswspimm7_2; assign l2[31:20] = ( l1[31:20] ) | - ( {12{simm5_0}} & {{7{simm5d[5]}},simm5d[4:0]} ) | - ( {12{uimm9_2}} & {2'b0,uimm9d[9:2],2'b0} ) | - ( {12{simm9_4}} & {{3{simm9d[9]}},simm9d[8:4],4'b0} ) | - ( {12{ulwimm6_2}} & {5'b0,ulwimm6d[6:2],2'b0} ) | - ( {12{ulwspimm7_2}} & {4'b0,ulwspimm7d[7:2],2'b0} ) | - ( {12{uimm5_0}} & {6'b0,uimm5d[5:0]} ) | - ( {12{sjaloffset11_1}} & {sjald[20],sjald[10:1],sjald[11]} ) | - ( {12{sluimm17_12}} & sluimmd[31:20] ); - + ( {12{simm5_0}} & {{7{simm5d[5]}},simm5d[4:0]} ) | + ( {12{uimm9_2}} & {2'b0,uimm9d[9:2],2'b0} ) | + ( {12{simm9_4}} & {{3{simm9d[9]}},simm9d[8:4],4'b0} ) | + ( {12{ulwimm6_2}} & {5'b0,ulwimm6d[6:2],2'b0} ) | + ( {12{ulwspimm7_2}} & {4'b0,ulwspimm7d[7:2],2'b0} ) | + ( {12{uimm5_0}} & {6'b0,uimm5d[5:0]} ) | + ( {12{sjaloffset11_1}} & {sjald[20],sjald[10:1],sjald[11]} ) | + ( {12{sluimm17_12}} & sluimmd[31:20] ); + assign l2[19:12] = ( l1[19:12] ) | - ( {8{sjaloffset11_1}} & sjald[19:12] ) | - ( {8{sluimm17_12}} & sluimmd[19:12] ); + ( {8{sjaloffset11_1}} & sjald[19:12] ) | + ( {8{sluimm17_12}} & sluimmd[19:12] ); assign l2[11:0] = l1[11:0]; @@ -164,9 +164,9 @@ logic uswspimm7_2; // merge in branch offset and store immediates - logic [8:1] sbr8d; - logic [6:2] uswimm6d; - logic [7:2] uswspimm7d; + logic [8:1] sbr8d; + logic [6:2] uswimm6d; + logic [7:2] uswspimm7d; assign sbr8d[8:1] = { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] }; @@ -176,17 +176,17 @@ logic uswspimm7_2; assign uswspimm7d[7:2] = { i[8:7], i[12:9] }; assign l3[31:25] = ( l2[31:25] ) | - ( {7{sbroffset8_1}} & { {4{sbr8d[8]}},sbr8d[7:5] } ) | - ( {7{uswimm6_2}} & { 5'b0, uswimm6d[6:5] } ) | - ( {7{uswspimm7_2}} & { 4'b0, uswspimm7d[7:5] } ); + ( {7{sbroffset8_1}} & { {4{sbr8d[8]}},sbr8d[7:5] } ) | + ( {7{uswimm6_2}} & { 5'b0, uswimm6d[6:5] } ) | + ( {7{uswspimm7_2}} & { 4'b0, uswspimm7d[7:5] } ); assign l3[24:12] = l2[24:12]; assign l3[11:7] = ( l2[11:7] ) | - ( {5{sbroffset8_1}} & { sbr8d[4:1], sbr8d[8] } ) | - ( {5{uswimm6_2}} & { uswimm6d[4:2], 2'b0 } ) | - ( {5{uswspimm7_2}} & { uswspimm7d[4:2], 2'b0 } ); + ( {5{sbroffset8_1}} & { sbr8d[4:1], sbr8d[8] } ) | + ( {5{uswimm6_2}} & { uswimm6d[4:2], 2'b0 } ) | + ( {5{uswspimm7_2}} & { uswspimm7d[4:2], 2'b0 } ); assign l3[6:0] = l2[6:0]; diff --git a/design/ifu/ifu_ic_mem.sv b/design/ifu/ifu_ic_mem.sv index ace0997..dd8b845 100644 --- a/design/ifu/ifu_ic_mem.sv +++ b/design/ifu/ifu_ic_mem.sv @@ -212,12 +212,12 @@ module IC_DATA #(parameter ICACHE_TAG_HIGH = 16 , logic ic_debug_rd_en_ff; rvdff #(2) adr_ff (.*, - .din ({ic_rw_addr_q[5:4]}), - .dout({ic_rw_addr_ff[5:4]})); + .din ({ic_rw_addr_q[5:4]}), + .dout({ic_rw_addr_ff[5:4]})); rvdff #(5) debug_rd_wy_ff (.*, - .din ({ic_debug_rd_way_en[3:0], ic_debug_rd_en}), - .dout({ic_debug_rd_way_en_ff[3:0], ic_debug_rd_en_ff})); + .din ({ic_debug_rd_way_en[3:0], ic_debug_rd_en}), + .dout({ic_debug_rd_way_en_ff[3:0], ic_debug_rd_en_ff})); localparam NUM_WAYS=4 ; localparam NUM_SUBBANKS=4 ; @@ -225,29 +225,29 @@ localparam NUM_SUBBANKS=4 ; for (genvar i=0; i 0; i-- ) begin : find_first_one - done |= din[i]; - dout[SHIFT-1:0] += done ? 1'b0 : 1'b1; + done |= din[i]; + dout[SHIFT-1:0] += done ? 1'b0 : 1'b1; end : find_first_one end endmodule // rvfindfirst1 @@ -292,14 +292,14 @@ module rvfindfirst1hot #( parameter WIDTH=32 ) output logic [WIDTH-1:0] dout ); - logic done; + logic done; always_comb begin dout[WIDTH-1:0] = {WIDTH{1'b0}}; done = 1'b0; for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one - dout[i] = ~done & din[i]; - done |= din[i]; + dout[i] = ~done & din[i]; + done |= din[i]; end : find_first_one end endmodule // rvfindfirst1hot @@ -314,13 +314,13 @@ module rvmaskandmatch #( parameter WIDTH=32 ) output logic match ); - logic [WIDTH-1:0] matchvec; - logic masken_or_fullmask; + logic [WIDTH-1:0] matchvec; + logic masken_or_fullmask; assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]); assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]); - genvar i; + genvar i; for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]); @@ -331,45 +331,45 @@ module rvmaskandmatch #( parameter WIDTH=32 ) endmodule // rvmaskandmatch module rvbtb_tag_hash ( - input logic [31:1] pc, - output logic [`RV_BTB_BTAG_SIZE-1:0] hash - ); + input logic [31:1] pc, + output logic [`RV_BTB_BTAG_SIZE-1:0] hash + ); `ifndef RV_BTB_BTAG_FOLD assign hash = {(pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE+1] ^ - pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^ - pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])}; + pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^ + pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])}; `else assign hash = {( - pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^ - pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])}; + pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^ + pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])}; `endif // assign hash = {pc[`RV_BTB_ADDR_HI+1],(pc[`RV_BTB_ADDR_HI+13:`RV_BTB_ADDR_HI+10] ^ -// pc[`RV_BTB_ADDR_HI+9:`RV_BTB_ADDR_HI+6] ^ -// pc[`RV_BTB_ADDR_HI+5:`RV_BTB_ADDR_HI+2])}; +// pc[`RV_BTB_ADDR_HI+9:`RV_BTB_ADDR_HI+6] ^ +// pc[`RV_BTB_ADDR_HI+5:`RV_BTB_ADDR_HI+2])}; endmodule module rvbtb_addr_hash ( - input logic [31:1] pc, - output logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hash - ); + input logic [31:1] pc, + output logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hash + ); assign hash[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] = pc[`RV_BTB_INDEX1_HI:`RV_BTB_INDEX1_LO] ^ -`ifndef RV_BTB_FOLD2_INDEX_HASH - pc[`RV_BTB_INDEX2_HI:`RV_BTB_INDEX2_LO] ^ +`ifndef RV_BTB_FOLD2_INDEX_HASH + pc[`RV_BTB_INDEX2_HI:`RV_BTB_INDEX2_LO] ^ `endif - - pc[`RV_BTB_INDEX3_HI:`RV_BTB_INDEX3_LO]; + + pc[`RV_BTB_INDEX3_HI:`RV_BTB_INDEX3_LO]; endmodule module rvbtb_ghr_hash ( - input logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hashin, - input logic [`RV_BHT_GHR_RANGE] ghr, - output logic [`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO] hash - ); + input logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hashin, + input logic [`RV_BHT_GHR_RANGE] ghr, + output logic [`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO] hash + ); // The hash function is too complex to write in verilog for all cases. // The config script generates the logic string based on the bp config. @@ -405,28 +405,28 @@ endmodule // rvrangechecker // 16 bit even parity generator module rveven_paritygen #(WIDTH = 16) ( - input logic [WIDTH-1:0] data_in, // Data - output logic parity_out // generated even parity - ); + input logic [WIDTH-1:0] data_in, // Data + output logic parity_out // generated even parity + ); assign parity_out = ^(data_in[WIDTH-1:0]) ; endmodule // rveven_paritygen module rveven_paritycheck #(WIDTH = 16) ( - input logic [WIDTH-1:0] data_in, // Data - input logic parity_in, - output logic parity_err // Parity error - ); + input logic [WIDTH-1:0] data_in, // Data + input logic parity_in, + output logic parity_err // Parity error + ); assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ; endmodule // rveven_paritycheck module rvecc_encode ( - input [31:0] din, - output [6:0] ecc_out - ); + input [31:0] din, + output [6:0] ecc_out + ); logic [5:0] ecc_out_temp; assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; @@ -441,20 +441,20 @@ logic [5:0] ecc_out_temp; endmodule // rvecc_encode module rvecc_decode ( - input en, - input [31:0] din, - input [6:0] ecc_in, + input en, + input [31:0] din, + input [6:0] ecc_in, input sed_ded, // only do detection and no correction. Used for the I$ - output [31:0] dout, + output [31:0] dout, output [6:0] ecc_out, - output single_ecc_error, - output double_ecc_error + output single_ecc_error, + output double_ecc_error - ); + ); - logic [6:0] ecc_check; - logic [38:0] error_mask; - logic [38:0] din_plus_parity, dout_plus_parity; + logic [6:0] ecc_check; + logic [38:0] error_mask; + logic [38:0] din_plus_parity, dout_plus_parity; // Generate the ecc bits assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; diff --git a/design/lib/mem_lib.sv b/design/lib/mem_lib.sv index daa8cab..ccd0961 100644 --- a/design/lib/mem_lib.sv +++ b/design/lib/mem_lib.sv @@ -27,12 +27,12 @@ module ram_32768x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [32767:0]; + reg [38:0] ram_core [32767:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -51,12 +51,12 @@ module ram_16384x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [16383:0]; + reg [38:0] ram_core [16383:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -74,12 +74,12 @@ module ram_8192x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [8191:0]; + reg [38:0] ram_core [8191:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -97,12 +97,12 @@ module ram_4096x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [4095:0]; + reg [38:0] ram_core [4095:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -120,12 +120,12 @@ module ram_3072x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [3071:0]; + reg [38:0] ram_core [3071:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -145,12 +145,12 @@ module ram_2048x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [2047:0]; + reg [38:0] ram_core [2047:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -168,12 +168,12 @@ module ram_1536x39 // need this for the 48KB DCCM option // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [1535:0]; + reg [38:0] ram_core [1535:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -192,12 +192,12 @@ module ram_1024x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [1023:0]; + reg [38:0] ram_core [1023:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -215,12 +215,12 @@ module ram_768x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [767:0]; + reg [38:0] ram_core [767:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -239,12 +239,12 @@ module ram_512x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [511:0]; + reg [38:0] ram_core [511:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -263,12 +263,12 @@ module ram_256x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [255:0]; + reg [38:0] ram_core [255:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -287,12 +287,12 @@ module ram_128x39 // behavior to be replaced by actual SRAM in VLE - reg [38:0] ram_core [127:0]; + reg [38:0] ram_core [127:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -314,12 +314,12 @@ module ram_1024x20 // behavior to be replaced by actual SRAM in VLE - reg [19:0] ram_core [1023:0]; + reg [19:0] ram_core [1023:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -336,12 +336,12 @@ module ram_512x20 // behavior to be replaced by actual SRAM in VLE - reg [19:0] ram_core [511:0]; + reg [19:0] ram_core [511:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -359,12 +359,12 @@ module ram_256x20 // behavior to be replaced by actual SRAM in VLE - reg [19:0] ram_core [255:0]; + reg [19:0] ram_core [255:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -381,12 +381,12 @@ module ram_128x20 // behavior to be replaced by actual SRAM in VLE - reg [19:0] ram_core [127:0]; + reg [19:0] ram_core [127:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -404,12 +404,12 @@ module ram_64x20 // behavior to be replaced by actual SRAM in VLE - reg [19:0] ram_core [63:0]; + reg [19:0] ram_core [63:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -431,12 +431,12 @@ module ram_4096x34 // behavior to be replaced by actual SRAM in VLE - reg [33:0] ram_core [4095:0]; + reg [33:0] ram_core [4095:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -456,12 +456,12 @@ module ram_2048x34 // behavior to be replaced by actual SRAM in VLE - reg [33:0] ram_core [2047:0]; + reg [33:0] ram_core [2047:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -481,12 +481,12 @@ module ram_1024x34 // behavior to be replaced by actual SRAM in VLE - reg [33:0] ram_core [1023:0]; + reg [33:0] ram_core [1023:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -506,12 +506,12 @@ module ram_512x34 // behavior to be replaced by actual SRAM in VLE - reg [33:0] ram_core [511:0]; + reg [33:0] ram_core [511:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -531,12 +531,12 @@ module ram_256x34 // behavior to be replaced by actual SRAM in VLE - reg [33:0] ram_core [255:0]; + reg [33:0] ram_core [255:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -556,12 +556,12 @@ module ram_128x34 // behavior to be replaced by actual SRAM in VLE - reg [33:0] ram_core [127:0]; + reg [33:0] ram_core [127:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -580,12 +580,12 @@ module ram_64x34 // behavior to be replaced by actual SRAM in VLE - reg [33:0] ram_core [63:0]; + reg [33:0] ram_core [63:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -607,12 +607,12 @@ module ram_4096x42 // behavior to be replaced by actual SRAM in VLE - reg [41:0] ram_core [4095:0]; + reg [41:0] ram_core [4095:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -632,12 +632,12 @@ module ram_2048x42 // behavior to be replaced by actual SRAM in VLE - reg [41:0] ram_core [2047:0]; + reg [41:0] ram_core [2047:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -656,12 +656,12 @@ module ram_1024x42 // behavior to be replaced by actual SRAM in VLE - reg [41:0] ram_core [1023:0]; + reg [41:0] ram_core [1023:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -680,12 +680,12 @@ module ram_512x42 // behavior to be replaced by actual SRAM in VLE - reg [41:0] ram_core [511:0]; + reg [41:0] ram_core [511:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -706,12 +706,12 @@ module ram_256x42 // behavior to be replaced by actual SRAM in VLE - reg [41:0] ram_core [255:0]; + reg [41:0] ram_core [255:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -731,12 +731,12 @@ module ram_128x42 // behavior to be replaced by actual SRAM in VLE - reg [41:0] ram_core [127:0]; + reg [41:0] ram_core [127:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -756,12 +756,12 @@ module ram_64x42 // behavior to be replaced by actual SRAM in VLE - reg [41:0] ram_core [63:0]; + reg [41:0] ram_core [63:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -784,12 +784,12 @@ module ram_1024x21 // behavior to be replaced by actual SRAM in VLE - reg [20:0] ram_core [1023:0]; + reg [20:0] ram_core [1023:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -807,12 +807,12 @@ module ram_512x21 // behavior to be replaced by actual SRAM in VLE - reg [20:0] ram_core [511:0]; + reg [20:0] ram_core [511:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -832,12 +832,12 @@ module ram_256x21 // behavior to be replaced by actual SRAM in VLE - reg [20:0] ram_core [255:0]; + reg [20:0] ram_core [255:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -857,12 +857,12 @@ module ram_128x21 // behavior to be replaced by actual SRAM in VLE - reg [20:0] ram_core [127:0]; + reg [20:0] ram_core [127:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -882,12 +882,12 @@ module ram_64x21 // behavior to be replaced by actual SRAM in VLE - reg [20:0] ram_core [63:0]; + reg [20:0] ram_core [63:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -906,12 +906,12 @@ module ram_1024x25 // behavior to be replaced by actual SRAM in VLE - reg [24:0] ram_core [1023:0]; + reg [24:0] ram_core [1023:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -932,12 +932,12 @@ module ram_512x25 // behavior to be replaced by actual SRAM in VLE - reg [24:0] ram_core [511:0]; + reg [24:0] ram_core [511:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -958,12 +958,12 @@ module ram_256x25 // behavior to be replaced by actual SRAM in VLE - reg [24:0] ram_core [255:0]; + reg [24:0] ram_core [255:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -984,12 +984,12 @@ module ram_128x25 // behavior to be replaced by actual SRAM in VLE - reg [24:0] ram_core [127:0]; + reg [24:0] ram_core [127:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end @@ -1010,12 +1010,12 @@ module ram_64x25 // behavior to be replaced by actual SRAM in VLE - reg [24:0] ram_core [63:0]; + reg [24:0] ram_core [63:0]; always_ff @(posedge CLK) begin if (WE) begin// for active high WE - must be specified by user - ram_core[ADR] <= D; Q <= 'x; end else - Q <= ram_core[ADR]; + ram_core[ADR] <= D; Q <= 'x; end else + Q <= ram_core[ADR]; end diff --git a/design/lsu/lsu.sv b/design/lsu/lsu.sv index c5f915b..f984bc0 100644 --- a/design/lsu/lsu.sv +++ b/design/lsu/lsu.sv @@ -70,7 +70,7 @@ module lsu output logic [31:0] lsu_imprecise_error_addr_any, // bus store imprecise error address // Non-blocking loads - input logic dec_nonblock_load_freeze_dc2, // + input logic dec_nonblock_load_freeze_dc2, // output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads diff --git a/design/lsu/lsu_addrcheck.sv b/design/lsu/lsu_addrcheck.sv index 6bc483b..6a7f097 100644 --- a/design/lsu/lsu_addrcheck.sv +++ b/design/lsu/lsu_addrcheck.sv @@ -27,7 +27,7 @@ module lsu_addrcheck ( input logic lsu_freeze_c2_dc2_clk, // clock input logic lsu_freeze_c2_dc3_clk, - input logic rst_l, // reset + input logic rst_l, // reset input logic [31:0] start_addr_dc1, // start address for lsu input logic [31:0] end_addr_dc1, // end address for lsu @@ -44,7 +44,7 @@ module lsu_addrcheck output logic access_fault_dc1, // access fault output logic misaligned_fault_dc1, // misaligned - input logic scan_mode + input logic scan_mode ); `include "global.h" @@ -66,11 +66,11 @@ module lsu_addrcheck `endif logic is_sideeffects_dc1, is_aligned_dc1; - logic start_addr_in_dccm_dc1, end_addr_in_dccm_dc1; + logic start_addr_in_dccm_dc1, end_addr_in_dccm_dc1; logic start_addr_in_dccm_region_dc1, end_addr_in_dccm_region_dc1; - logic start_addr_in_pic_dc1, end_addr_in_pic_dc1; + logic start_addr_in_pic_dc1, end_addr_in_pic_dc1; logic start_addr_in_pic_region_dc1, end_addr_in_pic_region_dc1; - logic [4:0] csr_idx; + logic [4:0] csr_idx; logic addr_in_iccm; logic non_dccm_access_ok; @@ -119,10 +119,10 @@ module lsu_addrcheck .in_region(end_addr_in_pic_region_dc1) ); - assign addr_in_dccm_dc1 = (start_addr_in_dccm_dc1 & end_addr_in_dccm_dc1); - assign addr_in_pic_dc1 = (start_addr_in_pic_dc1 & end_addr_in_pic_dc1); + assign addr_in_dccm_dc1 = (start_addr_in_dccm_dc1 & end_addr_in_dccm_dc1); + assign addr_in_pic_dc1 = (start_addr_in_pic_dc1 & end_addr_in_pic_dc1); - assign addr_external_dc1 = ~(addr_in_dccm_dc1 | addr_in_pic_dc1); //~addr_in_dccm_region_dc1; + assign addr_external_dc1 = ~(addr_in_dccm_dc1 | addr_in_pic_dc1); //~addr_in_dccm_region_dc1; assign csr_idx[4:0] = {start_addr_dc1[31:28], 1'b1}; assign is_sideeffects_dc1 = dec_tlu_mrac_ff[csr_idx] & ~(start_addr_in_dccm_region_dc1 | start_addr_in_pic_region_dc1 | addr_in_iccm); //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions assign is_aligned_dc1 = (lsu_pkt_dc1.word & (start_addr_dc1[1:0] == 2'b0)) | @@ -134,7 +134,7 @@ module lsu_addrcheck (((`RV_DATA_ACCESS_ENABLE0 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK0)) == (`RV_DATA_ACCESS_ADDR0 | `RV_DATA_ACCESS_MASK0)) | (`RV_DATA_ACCESS_ENABLE1 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK1)) == (`RV_DATA_ACCESS_ADDR1 | `RV_DATA_ACCESS_MASK1)) | (`RV_DATA_ACCESS_ENABLE2 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK2)) == (`RV_DATA_ACCESS_ADDR2 | `RV_DATA_ACCESS_MASK2)) | - (`RV_DATA_ACCESS_ENABLE3 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK3)) == (`RV_DATA_ACCESS_ADDR3 | `RV_DATA_ACCESS_MASK3)) | + (`RV_DATA_ACCESS_ENABLE3 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK3)) == (`RV_DATA_ACCESS_ADDR3 | `RV_DATA_ACCESS_MASK3)) | (`RV_DATA_ACCESS_ENABLE4 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK4)) == (`RV_DATA_ACCESS_ADDR4 | `RV_DATA_ACCESS_MASK4)) | (`RV_DATA_ACCESS_ENABLE5 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK5)) == (`RV_DATA_ACCESS_ADDR5 | `RV_DATA_ACCESS_MASK5)) | (`RV_DATA_ACCESS_ENABLE6 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK6)) == (`RV_DATA_ACCESS_ADDR6 | `RV_DATA_ACCESS_MASK6)) | @@ -178,6 +178,6 @@ module lsu_addrcheck rvdff #(.WIDTH(1)) is_sideeffects_dc2ff (.din(is_sideeffects_dc1), .dout(is_sideeffects_dc2), .clk(lsu_freeze_c2_dc2_clk), .*); rvdff #(.WIDTH(1)) is_sideeffects_dc3ff (.din(is_sideeffects_dc2), .dout(is_sideeffects_dc3), .clk(lsu_freeze_c2_dc3_clk), .*); - + endmodule // lsu_addrcheck diff --git a/design/lsu/lsu_bus_buffer.sv b/design/lsu/lsu_bus_buffer.sv index a7fc5e8..09df1a6 100644 --- a/design/lsu/lsu_bus_buffer.sv +++ b/design/lsu/lsu_bus_buffer.sv @@ -118,7 +118,7 @@ module lsu_bus_buffer output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error // Non-blocking loads - input logic dec_nonblock_load_freeze_dc2, + input logic dec_nonblock_load_freeze_dc2, output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads @@ -126,7 +126,7 @@ module lsu_bus_buffer output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam output logic lsu_nonblock_load_data_error, // non block load has an error output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error - output logic [31:0] lsu_nonblock_load_data, // Data of the non block load + output logic [31:0] lsu_nonblock_load_data, // Data of the non block load // PMU events output logic lsu_pmu_bus_trxn, @@ -246,7 +246,7 @@ module lsu_bus_buffer // Bus buffer signals state_t [DEPTH-1:0] buf_state; - logic [DEPTH-1:0][2:0] buf_state_out; + logic [DEPTH-1:0][2:0] buf_state_out; logic [DEPTH-1:0][1:0] buf_sz; logic [DEPTH-1:0][31:0] buf_addr; logic [DEPTH-1:0][3:0] buf_byteen; @@ -666,12 +666,12 @@ module lsu_bus_buffer buf_error_en[i] = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag == LSU_BUS_TAG'(i))) | (bus_rsp_write_error & (bus_rsp_write_tag == LSU_BUS_TAG'(i)))); buf_data_in[i][31:0] = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0]; - end + end DONE: begin buf_nxtstate[i] = IDLE; buf_rst[i] = lsu_bus_clk_en_q & (buf_write[i] | ~buf_dual[i] | (buf_state[buf_dualtag[i]] == DONE)); buf_state_en[i] = buf_rst[i]; - end + end default : begin buf_nxtstate[i] = IDLE; buf_state_en[i] = '0; diff --git a/design/lsu/lsu_bus_intf.sv b/design/lsu/lsu_bus_intf.sv index fd27252..eff96ad 100644 --- a/design/lsu/lsu_bus_intf.sv +++ b/design/lsu/lsu_bus_intf.sv @@ -105,7 +105,7 @@ module lsu_bus_intf output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error // Non-blocking loads - input logic dec_nonblock_load_freeze_dc2, + input logic dec_nonblock_load_freeze_dc2, output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads @@ -113,7 +113,7 @@ module lsu_bus_intf output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam output logic lsu_nonblock_load_data_error, // non block load has an error output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error - output logic [31:0] lsu_nonblock_load_data, // Data of the non block load + output logic [31:0] lsu_nonblock_load_data, // Data of the non block load // PMU events output logic lsu_pmu_bus_trxn, @@ -173,7 +173,7 @@ module lsu_bus_intf `include "global.h" - logic ld_freeze_dc3; + logic ld_freeze_dc3; logic lsu_bus_clk_en_q; logic ldst_dual_dc1, ldst_dual_dc2, ldst_dual_dc3, ldst_dual_dc4, ldst_dual_dc5; @@ -181,8 +181,8 @@ module lsu_bus_intf logic [3:0] ldst_byteen_dc2, ldst_byteen_dc3, ldst_byteen_dc4, ldst_byteen_dc5; logic [7:0] ldst_byteen_ext_dc2, ldst_byteen_ext_dc3, ldst_byteen_ext_dc4, ldst_byteen_ext_dc5; - logic [3:0] ldst_byteen_hi_dc2, ldst_byteen_hi_dc3, ldst_byteen_hi_dc4, ldst_byteen_hi_dc5; - logic [3:0] ldst_byteen_lo_dc2, ldst_byteen_lo_dc3, ldst_byteen_lo_dc4, ldst_byteen_lo_dc5; + logic [3:0] ldst_byteen_hi_dc2, ldst_byteen_hi_dc3, ldst_byteen_hi_dc4, ldst_byteen_hi_dc5; + logic [3:0] ldst_byteen_lo_dc2, ldst_byteen_lo_dc3, ldst_byteen_lo_dc4, ldst_byteen_lo_dc5; logic is_sideeffects_dc4, is_sideeffects_dc5; @@ -198,12 +198,12 @@ module lsu_bus_intf logic ld_addr_dc4hit_lo_lo, ld_addr_dc4hit_hi_lo, ld_addr_dc4hit_lo_hi, ld_addr_dc4hit_hi_hi; logic ld_addr_dc5hit_lo_lo, ld_addr_dc5hit_hi_lo, ld_addr_dc5hit_lo_hi, ld_addr_dc5hit_hi_hi; - logic [3:0] ld_byte_dc3hit_lo_lo, ld_byte_dc3hit_hi_lo, ld_byte_dc3hit_lo_hi, ld_byte_dc3hit_hi_hi; - logic [3:0] ld_byte_dc4hit_lo_lo, ld_byte_dc4hit_hi_lo, ld_byte_dc4hit_lo_hi, ld_byte_dc4hit_hi_hi; - logic [3:0] ld_byte_dc5hit_lo_lo, ld_byte_dc5hit_hi_lo, ld_byte_dc5hit_lo_hi, ld_byte_dc5hit_hi_hi; + logic [3:0] ld_byte_dc3hit_lo_lo, ld_byte_dc3hit_hi_lo, ld_byte_dc3hit_lo_hi, ld_byte_dc3hit_hi_hi; + logic [3:0] ld_byte_dc4hit_lo_lo, ld_byte_dc4hit_hi_lo, ld_byte_dc4hit_lo_hi, ld_byte_dc4hit_hi_hi; + logic [3:0] ld_byte_dc5hit_lo_lo, ld_byte_dc5hit_hi_lo, ld_byte_dc5hit_lo_hi, ld_byte_dc5hit_hi_hi; - logic [3:0] ld_byte_hit_lo, ld_byte_dc3hit_lo, ld_byte_dc4hit_lo, ld_byte_dc5hit_lo; - logic [3:0] ld_byte_hit_hi, ld_byte_dc3hit_hi, ld_byte_dc4hit_hi, ld_byte_dc5hit_hi; + logic [3:0] ld_byte_hit_lo, ld_byte_dc3hit_lo, ld_byte_dc4hit_lo, ld_byte_dc5hit_lo; + logic [3:0] ld_byte_hit_hi, ld_byte_dc3hit_hi, ld_byte_dc4hit_hi, ld_byte_dc5hit_hi; logic [31:0] ld_fwddata_dc3pipe_lo, ld_fwddata_dc4pipe_lo, ld_fwddata_dc5pipe_lo; logic [31:0] ld_fwddata_dc3pipe_hi, ld_fwddata_dc4pipe_hi, ld_fwddata_dc5pipe_hi; @@ -381,7 +381,7 @@ module lsu_bus_intf assign {ld_fwddata_dc2_nc[63:32], ld_fwddata_dc2[31:0]} = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_dc2[1:0]); assign bus_read_data_dc3[31:0] = ld_full_hit_dc3 ? ld_fwddata_dc3[31:0] : ld_bus_data_dc3[31:0]; - + // Fifo flops rvdff #(.WIDTH(1)) lsu_full_hit_dc3ff (.din(ld_full_hit_dc2), .dout(ld_full_hit_dc3), .clk(lsu_freeze_c2_dc3_clk), .*); rvdff #(.WIDTH(32)) lsu_fwddata_dc3ff (.din(ld_fwddata_dc2[31:0]), .dout(ld_fwddata_dc3[31:0]), .clk(lsu_c1_dc3_clk), .*); diff --git a/design/lsu/lsu_dccm_ctl.sv b/design/lsu/lsu_dccm_ctl.sv index b02dc94..4bb553a 100644 --- a/design/lsu/lsu_dccm_ctl.sv +++ b/design/lsu/lsu_dccm_ctl.sv @@ -37,7 +37,7 @@ module lsu_dccm_ctl input logic rst_l, input logic clk, input logic lsu_freeze_dc3, // freze - + input lsu_pkt_t lsu_pkt_dc3, // lsu packets input lsu_pkt_t lsu_pkt_dc1, input logic addr_in_dccm_dc1, // address maps to dccm @@ -75,7 +75,7 @@ module lsu_dccm_ctl output logic dccm_dma_rvalid, // dccm serviving the dma load output logic dccm_dma_ecc_error, // DMA load had ecc error output logic [63:0] dccm_dma_rdata, // dccm data to dma request - + // DCCM ports output logic dccm_wren, // dccm interface -- write output logic dccm_rden, // dccm interface -- write @@ -83,7 +83,7 @@ module lsu_dccm_ctl output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_lo, // dccm interface -- read address for lo bank output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_hi, // dccm interface -- read address for hi bank output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data, // dccm write data - + input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // dccm read data back from the dccm input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // dccm read data back from the dccm @@ -95,7 +95,7 @@ module lsu_dccm_ctl output logic [31:0] picm_wr_data, // write data input logic [31:0] picm_rd_data, // read data - input logic scan_mode // scan mode + input logic scan_mode // scan mode ); `include "global.h" diff --git a/design/lsu/lsu_dccm_mem.sv b/design/lsu/lsu_dccm_mem.sv index 30a6ae4..e802cfb 100644 --- a/design/lsu/lsu_dccm_mem.sv +++ b/design/lsu/lsu_dccm_mem.sv @@ -29,8 +29,8 @@ module lsu_dccm_mem import swerv_types::*; ( - input logic clk, // clock - input logic rst_l, + input logic clk, // clock + input logic rst_l, input logic lsu_freeze_dc3, // freeze input logic clk_override, // clock override @@ -40,7 +40,7 @@ module lsu_dccm_mem input logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_lo, // read address input logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data, // write data - + output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank @@ -52,16 +52,16 @@ module lsu_dccm_mem localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH); localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS); - logic [DCCM_NUM_BANKS-1:0] wren_bank; - logic [DCCM_NUM_BANKS-1:0] rden_bank; + logic [DCCM_NUM_BANKS-1:0] wren_bank; + logic [DCCM_NUM_BANKS-1:0] rden_bank; logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank; logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd; logic rd_unaligned; logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout; logic [DCCM_FDATA_WIDTH-1:0] wrdata; - logic [DCCM_NUM_BANKS-1:0] wren_bank_q; - logic [DCCM_NUM_BANKS-1:0] rden_bank_q; + logic [DCCM_NUM_BANKS-1:0] wren_bank_q; + logic [DCCM_NUM_BANKS-1:0] rden_bank_q; logic [DCCM_NUM_BANKS-1:0][DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank_q; logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_q; diff --git a/design/lsu/lsu_ecc.sv b/design/lsu/lsu_ecc.sv index 33c38d4..cc6a04e 100644 --- a/design/lsu/lsu_ecc.sv +++ b/design/lsu/lsu_ecc.sv @@ -47,7 +47,7 @@ module lsu_ecc input logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_dc3, // data forward from the store buffer input logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_dc3,// which bytes from the store buffer are on input logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_dc3,// which bytes from the store buffer are on - + input logic [`RV_DCCM_DATA_WIDTH-1:0] dccm_data_hi_dc3, // raw data from mem input logic [`RV_DCCM_DATA_WIDTH-1:0] dccm_data_lo_dc3, // raw data from mem input logic [`RV_DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_dc3, // ecc read out from mem @@ -64,7 +64,7 @@ module lsu_ecc output logic lsu_single_ecc_error_dc3, // or of the 2 output logic lsu_double_ecc_error_dc3, // double error detected - input logic scan_mode + input logic scan_mode ); `include "global.h" @@ -84,14 +84,14 @@ module lsu_ecc logic ldst_dual_dc3; logic is_ldst_dc3; logic is_ldst_hi_dc3, is_ldst_lo_dc3; - logic [7:0] ldst_byteen_dc3; - logic [7:0] store_byteen_dc3; + logic [7:0] ldst_byteen_dc3; + logic [7:0] store_byteen_dc3; logic [7:0] store_byteen_ext_dc3; - logic [DCCM_BYTE_WIDTH-1:0] store_byteen_hi_dc3, store_byteen_lo_dc3; + logic [DCCM_BYTE_WIDTH-1:0] store_byteen_hi_dc3, store_byteen_lo_dc3; logic [163:0] store_data_ext_dc3; logic [DCCM_DATA_WIDTH-1:0] store_data_hi_dc3, store_data_lo_dc3; - logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc; + logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc; assign ldst_dual_dc3 = (lsu_addr_dc3[2] != end_addr_dc3[2]); @@ -128,28 +128,28 @@ module lsu_ecc rvecc_decode lsu_ecc_decode_hi ( // Inputs .en(is_ldst_hi_dc3), - .sed_ded (1'b0), // 1 : means only detection + .sed_ded (1'b0), // 1 : means only detection .din(dccm_data_hi_dc3[DCCM_DATA_WIDTH-1:0]), .ecc_in(dccm_data_ecc_hi_dc3[DCCM_ECC_WIDTH-1:0]), // Outputs .dout(sec_data_hi_dc3[DCCM_DATA_WIDTH-1:0]), - .ecc_out (ecc_out_hi_nc[6:0]), - .single_ecc_error(single_ecc_error_hi_dc3), - .double_ecc_error(double_ecc_error_hi_dc3), + .ecc_out (ecc_out_hi_nc[6:0]), + .single_ecc_error(single_ecc_error_hi_dc3), + .double_ecc_error(double_ecc_error_hi_dc3), .* ); rvecc_decode lsu_ecc_decode_lo ( - // Inputs + // Inputs .en(is_ldst_lo_dc3), - .sed_ded (1'b0), // 1 : means only detection + .sed_ded (1'b0), // 1 : means only detection .din(dccm_data_lo_dc3[DCCM_DATA_WIDTH-1:0] ), .ecc_in(dccm_data_ecc_lo_dc3[DCCM_ECC_WIDTH-1:0]), // Outputs .dout(sec_data_lo_dc3[DCCM_DATA_WIDTH-1:0]), .ecc_out (ecc_out_lo_nc[6:0]), - .single_ecc_error(single_ecc_error_lo_dc3), - .double_ecc_error(double_ecc_error_lo_dc3), + .single_ecc_error(single_ecc_error_lo_dc3), + .double_ecc_error(double_ecc_error_lo_dc3), .* ); diff --git a/design/lsu/lsu_stbuf.sv b/design/lsu/lsu_stbuf.sv index d3edff6..49a2cf9 100644 --- a/design/lsu/lsu_stbuf.sv +++ b/design/lsu/lsu_stbuf.sv @@ -47,7 +47,7 @@ module lsu_stbuf input logic lsu_stbuf_c1_clk, // stbuf clock input logic lsu_free_c2_clk, // free clk - // Store Buffer input + // Store Buffer input input logic load_stbuf_reqvld_dc3, // core instruction goes to stbuf input logic store_stbuf_reqvld_dc3, // core instruction goes to stbuf //input logic ldst_stbuf_reqvld_dc3, @@ -61,14 +61,14 @@ module lsu_stbuf input logic isldst_dc1, // instruction in dc1 is lsu input logic dccm_ldst_dc2, // instruction in dc2 is lsu input logic dccm_ldst_dc3, // instruction in dc3 is lsu - - input logic single_ecc_error_hi_dc3, // single ecc error in hi bank - input logic single_ecc_error_lo_dc3, // single ecc error in lo bank + + input logic single_ecc_error_hi_dc3, // single ecc error in hi bank + input logic single_ecc_error_lo_dc3, // single ecc error in lo bank input logic lsu_single_ecc_error_dc5, // single_ecc_error in either bank staged to the dc5 - needed for the load repairs input logic lsu_commit_dc5, // lsu commits input logic lsu_freeze_dc3, // lsu freeze input logic flush_prior_dc5, // Flush is due to i0 and ld/st is in i1 - + // Store Buffer output output logic stbuf_reqvld_any, // stbuf is draining output logic stbuf_reqvld_flushed_any, // Top entry is flushed @@ -85,16 +85,16 @@ module lsu_stbuf input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc1, // lsu address input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc2, input logic [`RV_LSU_SB_BITS-1:0] lsu_addr_dc3, - + input logic [`RV_LSU_SB_BITS-1:0] end_addr_dc1, // lsu end addrress - needed to check unaligned input logic [`RV_LSU_SB_BITS-1:0] end_addr_dc2, input logic [`RV_LSU_SB_BITS-1:0] end_addr_dc3, - + // Forwarding signals input logic lsu_cmpen_dc2, // needed for forwarding stbuf - load input lsu_pkt_t lsu_pkt_dc2, - input lsu_pkt_t lsu_pkt_dc3, - input lsu_pkt_t lsu_pkt_dc5, + input lsu_pkt_t lsu_pkt_dc3, + input lsu_pkt_t lsu_pkt_dc5, output logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_dc3, // stbuf data output logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_dc3, @@ -102,7 +102,7 @@ module lsu_stbuf output logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_dc3, input logic scan_mode - + ); `include "global.h" @@ -121,19 +121,19 @@ module lsu_stbuf logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteen; logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_data; - logic [DEPTH-1:0] sel_lo; - logic [DEPTH-1:0] stbuf_wr_en; - logic [DEPTH-1:0] stbuf_data_en; - logic [DEPTH-1:0] stbuf_drain_or_flush_en; - logic [DEPTH-1:0] stbuf_flush_en; - logic [DEPTH-1:0] stbuf_drain_en; - logic [DEPTH-1:0] stbuf_reset; + logic [DEPTH-1:0] sel_lo; + logic [DEPTH-1:0] stbuf_wr_en; + logic [DEPTH-1:0] stbuf_data_en; + logic [DEPTH-1:0] stbuf_drain_or_flush_en; + logic [DEPTH-1:0] stbuf_flush_en; + logic [DEPTH-1:0] stbuf_drain_en; + logic [DEPTH-1:0] stbuf_reset; logic [DEPTH-1:0][LSU_SB_BITS-1:0] stbuf_addrin; logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_datain; logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteenin; logic [7:0] ldst_byteen_dc3; - logic [7:0] store_byteen_ext_dc3; + logic [7:0] store_byteen_ext_dc3; logic [BYTE_WIDTH-1:0] store_byteen_hi_dc3; logic [BYTE_WIDTH-1:0] store_byteen_lo_dc3; @@ -150,8 +150,8 @@ module lsu_stbuf logic ldst_stbuf_reqvld_dc4, ldst_stbuf_reqvld_dc5; logic dual_stbuf_write_dc4, dual_stbuf_write_dc5; - logic [3:0] stbuf_numvld_any, stbuf_specvld_any; - logic [1:0] stbuf_specvld_dc1, stbuf_specvld_dc2, stbuf_specvld_dc3; + logic [3:0] stbuf_numvld_any, stbuf_specvld_any; + logic [1:0] stbuf_specvld_dc1, stbuf_specvld_dc2, stbuf_specvld_dc3; logic stbuf_oneavl_any, stbuf_twoavl_any; logic cmpen_hi_dc2, cmpen_lo_dc2, jit_in_same_region; @@ -169,7 +169,7 @@ module lsu_stbuf logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_fwdbyteenvec_hi, stbuf_fwdbyteenvec_lo; logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_fwddatavec_hi, stbuf_fwddatavec_lo; logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_dc2, stbuf_fwddata_lo_dc2; - logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_fn_dc2, stbuf_fwddata_lo_fn_dc2; + logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_fn_dc2, stbuf_fwddata_lo_fn_dc2; logic [BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_dc2, stbuf_fwdbyteen_lo_dc2; logic [BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_fn_dc2, stbuf_fwdbyteen_lo_fn_dc2; logic stbuf_load_repair_dc5; @@ -204,7 +204,7 @@ module lsu_stbuf (i == WrPtrPlus1[DEPTH_LOG2-1:0] & dual_stbuf_write_dc3)); assign stbuf_data_en[i] = stbuf_wr_en[i]; assign stbuf_drain_or_flush_en[i] = ldst_stbuf_reqvld_dc5 & ~lsu_pkt_dc5.dma & ((i == WrPtr_dc5[DEPTH_LOG2-1:0]) | - (i == WrPtrPlus1_dc5[DEPTH_LOG2-1:0] & dual_stbuf_write_dc5)); + (i == WrPtrPlus1_dc5[DEPTH_LOG2-1:0] & dual_stbuf_write_dc5)); assign stbuf_drain_en[i] = (stbuf_drain_or_flush_en[i] & (lsu_commit_dc5 | stbuf_load_repair_dc5)) | (stbuf_wr_en[i] & lsu_pkt_dc3.dma); assign stbuf_flush_en[i] = stbuf_drain_or_flush_en[i] & ~(lsu_commit_dc5 | stbuf_load_repair_dc5); assign stbuf_reset[i] = (lsu_stbuf_commit_any | stbuf_reqvld_flushed_any) & (i == RdPtr[DEPTH_LOG2-1:0]); @@ -303,7 +303,7 @@ module lsu_stbuf assign stbuf_fwddata_lo_hi[(8*i)+7:(8*i)] = {8{stbuf_fwdbyteen_lo_hi[i]}} & store_ecc_datafn_hi_dc3[(8*i)+7:(8*i)]; assign stbuf_fwddata_lo_lo[(8*i)+7:(8*i)] = {8{stbuf_fwdbyteen_lo_lo[i]}} & store_ecc_datafn_lo_dc3[(8*i)+7:(8*i)]; end - + always_comb begin: GenLdFwd stbuf_fwdbyteen_hi_dc2[BYTE_WIDTH-1:0] = '0; @@ -314,13 +314,13 @@ module lsu_stbuf stbuf_ldmatch_lo[i] = (stbuf_addr[i][LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] == cmpaddr_lo_dc2[LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) & (stbuf_drain_vld[i] | ~lsu_pkt_dc2.dma) & ~stbuf_flush_vld[i] & ((stbuf_addr_in_pic[i] & addr_in_pic_dc2) | (~stbuf_addr_in_pic[i] & addr_in_dccm_dc2)); - for (int j=0; j