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Branch for version 1.7

This commit is contained in:
Joseph Rahmeh 2020-06-25 19:59:36 -07:00
parent 0555dd8763
commit 8065eef677
29 changed files with 553 additions and 314 deletions
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13
README.md
View File

@ -1,6 +1,6 @@
# EH1 SweRV RISC-V Core<sup>TM</sup> 1.6 from Western Digital # EH1 SweRV RISC-V Core<sup>TM</sup> 1.7 from Western Digital
This repository contains the SweRV EH1 ver 1.6 Core<sup>TM</sup> design RTL This repository contains the SweRV EH1 Core<sup>TM</sup> design RTL
## License ## License
@ -28,7 +28,7 @@ Files under the [tools](tools/) directory may be available under a different lic
## Dependencies ## Dependencies
- Verilator **(4.020 or later)** must be installed on the system if running with verilator - Verilator **(4.030 or later)** must be installed on the system if running with verilator
- If adding/removing instructions, espresso must be installed (used by *tools/coredecode*) - If adding/removing instructions, espresso must be installed (used by *tools/coredecode*)
- RISCV tool chain (based on gcc version 7.3 or higher) must be - RISCV tool chain (based on gcc version 7.3 or higher) must be
installed so that it can be used to prepare RISCV binaries to run. installed so that it can be used to prepare RISCV binaries to run.
@ -192,7 +192,12 @@ The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tes
**Building an FPGA speed optimized model:** **Building an FPGA speed optimized model:**
Use ``-fpga_optimize=1`` option to ``swerv.config`` to build a model that is removes clock gating logic from flop model so that the FPGA builds can run a higher speeds. Use ``-fpga_optimize=1`` option to ``swerv.config`` to build a model that removes clock gating logic from flop model so that the FPGA builds can run at higher speeds. **This is now the default option for
targets other than ``default_pd``.**
**Building a Power optimized model (ASIC flows):**
Use ``-fpga_optimize=0`` option to ``swerv.config`` to build a model that **enables** clock gating logic into the flop model so that the ASIC flows get a better power footprint. **This is now the default option for
target``default_pd``.**
---- ----
Western Digital, the Western Digital logo, G-Technology, SanDisk, Tegile, Upthere, WD, SweRV Core, SweRV ISS, Western Digital, the Western Digital logo, G-Technology, SanDisk, Tegile, Upthere, WD, SweRV Core, SweRV ISS,

29
configs/swerv.config
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@ -270,6 +270,7 @@ if ($target eq "default") {
if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024 if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024
if (!defined($pic_size)) { $pic_size=32; } if (!defined($pic_size)) { $pic_size=32; }
if (!defined($pic_total_int)) { $pic_total_int=8; } if (!defined($pic_total_int)) { $pic_total_int=8; }
if (!defined($fpga_optimize)) { $fpga_optimize=1; }
# default is AXI bus # default is AXI bus
} }
@ -295,6 +296,7 @@ elsif ($target eq "default_ahb") {
if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024 if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024
if (!defined($pic_size)) { $pic_size=32; } if (!defined($pic_size)) { $pic_size=32; }
if (!defined($pic_total_int)) { $pic_total_int=8; } if (!defined($pic_total_int)) { $pic_total_int=8; }
if (!defined($fpga_optimize)) { $fpga_optimize=1; }
$ahb_lite = 1; $ahb_lite = 1;
} elsif ($target eq "default_pd") { } elsif ($target eq "default_pd") {
@ -319,6 +321,7 @@ elsif ($target eq "default_ahb") {
if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024 if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024
if (!defined($pic_size)) { $pic_size=32; } if (!defined($pic_size)) { $pic_size=32; }
if (!defined($pic_total_int)) { $pic_total_int=8; } if (!defined($pic_total_int)) { $pic_total_int=8; }
if (!defined($fpga_optimize)) { $fpga_optimize=0; }
} elsif ($target eq "high_perf") { } elsif ($target eq "high_perf") {
if (!defined($ret_stack_size)) { $ret_stack_size=4; } if (!defined($ret_stack_size)) { $ret_stack_size=4; }
@ -342,6 +345,7 @@ elsif ($target eq "default_ahb") {
if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024 if (!defined($pic_offset)) { $pic_offset="0xc0000"; } # 3*256*1024
if (!defined($pic_size)) { $pic_size=32; } if (!defined($pic_size)) { $pic_size=32; }
if (!defined($pic_total_int)) { $pic_total_int=8; } if (!defined($pic_total_int)) { $pic_total_int=8; }
if (!defined($fpga_optimize)) { $fpga_optimize=1; }
} else { } else {
die "$self: ERROR! Unsupported target \"$target\". Supported targets are: \"default, default_ahb, default_pd, high_perf\"!\n"; die "$self: ERROR! Unsupported target \"$target\". Supported targets are: \"default, default_ahb, default_pd, high_perf\"!\n";
@ -413,7 +417,7 @@ our %csr = (#{{{
"exists" => "true", "exists" => "true",
}, },
"mimpid" => { "mimpid" => {
"reset" => "0x3", "reset" => "0x4",
"mask" => "0x0", "mask" => "0x0",
"exists" => "true", "exists" => "true",
}, },
@ -890,7 +894,7 @@ our %config = (#{{{
"external_prog" => 'derived, overridable', # Testbench only "external_prog" => 'derived, overridable', # Testbench only
"debug_sb_mem" => 'derived, overridable', # Testbench only "debug_sb_mem" => 'derived, overridable', # Testbench only
"external_data_1" => 'derived, overridable', # Testbench only "external_data_1" => 'derived, overridable', # Testbench only
"external_mem_hole" => 'derived, overridable', # Testbench only "external_mem_hole" => 'default disabled', # Testbench only
# "consoleio" => 'derived', # Part of serial io. # "consoleio" => 'derived', # Part of serial io.
}, },
"bus" => { "bus" => {
@ -1376,10 +1380,12 @@ if (hex($config{protection}{data_access_enable0}) > 0 ||
hex($config{protection}{inst_access_enable4}) > 0 || hex($config{protection}{inst_access_enable4}) > 0 ||
hex($config{protection}{inst_access_enable5}) > 0 || hex($config{protection}{inst_access_enable5}) > 0 ||
hex($config{protection}{inst_access_enable6}) > 0 || hex($config{protection}{inst_access_enable6}) > 0 ||
hex($config{protection}{inst_access_enable7}) > 0) { hex($config{protection}{inst_access_enable7}) > 0 ||
$config{memmap}{external_mem_hole} eq "default disabled"){
delete($config{memmap}{external_mem_hole}) ; delete($config{memmap}{external_mem_hole}) ;
} else { } else {
# Unused region to create a memory map hole # Unused region to create a memory map hole, if not already specified
if ($config{memmap}{external_mem_hole} eq "derived, overridable") {
for (my $rgn = 15;$rgn >= 0; $rgn--) { for (my $rgn = 15;$rgn >= 0; $rgn--) {
if (!defined($regions_used{$rgn})) { if (!defined($regions_used{$rgn})) {
$config{memmap}{external_mem_hole} = ($rgn << 28); $config{memmap}{external_mem_hole} = ($rgn << 28);
@ -1387,15 +1393,11 @@ if (hex($config{protection}{data_access_enable0}) > 0 ||
last; last;
} }
} }
if ($config{memmap}{external_mem_hole} == 0) {
$config{protection}{data_access_addr0} = "0x10000000";
$config{protection}{data_access_mask0} = "0xffffffff";
$config{protection}{data_access_enable0} = "1";
} elsif (($config{memmap}{external_mem_hole}>>28) == 16) {
$config{protection}{data_access_addr0} = "0x00000000";
$config{protection}{data_access_mask0} = "0xefffffff";
$config{protection}{data_access_enable0} = "1";
} else { } else {
my $rgn = hex($config{memmap}{external_mem_hole})>>28;
$config{memmap}{external_mem_hole} = ($rgn << 28);
$regions_used{$rgn} =1;
}
my $hreg = $config{memmap}{external_mem_hole}>>28; my $hreg = $config{memmap}{external_mem_hole}>>28;
$config{protection}{data_access_addr0} = sprintf("0x%x", (($hreg^8)&8)<<28); $config{protection}{data_access_addr0} = sprintf("0x%x", (($hreg^8)&8)<<28);
$config{protection}{data_access_mask0} = "0x7fffffff"; $config{protection}{data_access_mask0} = "0x7fffffff";
@ -1421,10 +1423,11 @@ if (hex($config{protection}{data_access_enable0}) > 0 ||
$config{protection}{inst_access_enable1} = "1"; $config{protection}{inst_access_enable1} = "1";
$config{protection}{inst_access_enable2} = "1"; $config{protection}{inst_access_enable2} = "1";
$config{protection}{inst_access_enable3} = "1"; $config{protection}{inst_access_enable3} = "1";
}
$config{memmap}{external_mem_hole} = sprintf("0x%08x", $config{memmap}{external_mem_hole}); $config{memmap}{external_mem_hole} = sprintf("0x%08x", $config{memmap}{external_mem_hole});
} }
#Define 5 unused regions for used in TG #Define 5 unused regions for used in TG
foreach my $unr (reverse(0 .. 15)) { foreach my $unr (reverse(0 .. 15)) {

41
design/dbg/dbg.sv
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@ -161,6 +161,8 @@ module dbg (
logic dmcontrol_wren, dmcontrol_wren_Q; logic dmcontrol_wren, dmcontrol_wren_Q;
// command // command
logic command_wren; logic command_wren;
logic command_transfer_din;
logic command_postexec_din;
logic [31:0] command_din; logic [31:0] command_din;
// needed to send the read data back for dmi reads // needed to send the read data back for dmi reads
logic [31:0] dmi_reg_rdata_din; logic [31:0] dmi_reg_rdata_din;
@ -180,6 +182,7 @@ module dbg (
logic [2:0] sbcs_sberror_din; logic [2:0] sbcs_sberror_din;
logic sbcs_unaligned; logic sbcs_unaligned;
logic sbcs_illegal_size; logic sbcs_illegal_size;
logic [19:15] sbcs_reg_int;
// data // data
logic sbdata0_reg_wren0; logic sbdata0_reg_wren0;
@ -239,7 +242,10 @@ module dbg (
rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*); rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*);
rvoclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*); rvoclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*);
rvclkhdr bus_cgc (.en(bus_clken), .l1clk(bus_clk), .*);
`ifndef RV_FPGA_OPTIMIZE
rvclkhdr bus_cgc (.en(bus_clken), .l1clk(bus_clk), .*); // ifndef FPGA_OPTIMIZE
`endif
// end clocking section // end clocking section
@ -251,6 +257,7 @@ module dbg (
// sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal // sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal
assign sbcs_reg[31:29] = 3'b1; assign sbcs_reg[31:29] = 3'b1;
assign sbcs_reg[28:23] = '0; assign sbcs_reg[28:23] = '0;
assign sbcs_reg[19:15] = {sbcs_reg_int[19], ~sbcs_reg_int[18], sbcs_reg_int[17:15]};
assign sbcs_reg[11:5] = 7'h20; assign sbcs_reg[11:5] = 7'h20;
assign sbcs_reg[4:0] = 5'b01111; assign sbcs_reg[4:0] = 5'b01111;
assign sbcs_wren = (dmi_reg_addr == 7'h38) & dmi_reg_en & dmi_reg_wr_en & (sb_state == SBIDLE); // & (sbcs_reg[14:12] == 3'b000); assign sbcs_wren = (dmi_reg_addr == 7'h38) & dmi_reg_en & dmi_reg_wr_en & (sb_state == SBIDLE); // & (sbcs_reg[14:12] == 3'b000);
@ -261,7 +268,8 @@ module dbg (
rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(5) sbcs_misc_reg (.din(dmi_reg_wdata[19:15]), .dout(sbcs_reg[19:15]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); rvdffs #(5) sbcs_misc_reg (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),
.dout(sbcs_reg_int[19:15]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) | assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) |
@ -354,11 +362,14 @@ module dbg (
assign abstractcs_reg[7:4] = '0; assign abstractcs_reg[7:4] = '0;
assign abstractcs_reg[3:0] = 4'h2; // One data register assign abstractcs_reg[3:0] = 4'h2; // One data register
assign abstractcs_error_sel0 = abstractcs_reg[12] & dmi_reg_en & ((dmi_reg_wr_en & ( (dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17))) | (dmi_reg_addr == 7'h4)); assign abstractcs_error_sel0 = abstractcs_reg[12] & dmi_reg_en & ((dmi_reg_wr_en & ( (dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17))) | (dmi_reg_addr == 7'h4));
assign abstractcs_error_sel1 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h17) & ~((dmi_reg_wdata[31:24] == 8'b0) | (dmi_reg_wdata[31:24] == 8'h2)); assign abstractcs_error_sel1 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h17) &
((~((dmi_reg_wdata[31:24] == 8'b0) | (dmi_reg_wdata[31:24] == 8'h2))) | // Illegal command
((dmi_reg_wdata[22:20] != 3'b010) & ((dmi_reg_wdata[31:24] == 8'h2) | ((dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17]))) | // Illegal size
((dmi_reg_wdata[31:24] == 8'h0) & (dmi_reg_wdata[19] | dmi_reg_wdata[18])) | //aarpostincrement/postexec for abstract register access
((dmi_reg_wdata[31:24] == 8'h2) & dmi_reg_wdata[19])); //aampostincrement for abstract memory access
assign abstractcs_error_sel2 = core_dbg_cmd_done & core_dbg_cmd_fail; assign abstractcs_error_sel2 = core_dbg_cmd_done & core_dbg_cmd_fail;
assign abstractcs_error_sel3 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h17) & (dbg_state != HALTED); assign abstractcs_error_sel3 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h17) & (dbg_state != HALTED);
assign abstractcs_error_sel4 = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & assign abstractcs_error_sel4 = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & ((dmi_reg_wdata[31:24] == 8'h2) && (|data1_reg[1:0])); //Unaligned address for abstract memory
((dmi_reg_wdata[22:20] != 3'b010) | ((dmi_reg_wdata[31:24] == 8'h2) && (|data1_reg[1:0]))); // Only word size is allowed
assign abstractcs_error_sel5 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en; assign abstractcs_error_sel5 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en;
@ -379,7 +390,9 @@ module dbg (
// command register - implemented all the bits in this register // command register - implemented all the bits in this register
// command[16] = 1: write, 0: read // command[16] = 1: write, 0: read
assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & (dbg_state == HALTED); assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & (dbg_state == HALTED);
assign command_din[31:0] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:20],3'b0,dmi_reg_wdata[16:0]}; assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[18];
assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17];
assign command_din[31:0] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din, dmi_reg_wdata[16:0]};
rvdffe #(32) dmcommand_reg (.*, .din(command_din[31:0]), .dout(command_reg[31:0]), .en(command_wren), .rst_l(dbg_dm_rst_l)); rvdffe #(32) dmcommand_reg (.*, .din(command_din[31:0]), .dout(command_reg[31:0]), .en(command_wren), .rst_l(dbg_dm_rst_l));
// data0 reg // data0 reg
@ -434,8 +447,9 @@ module dbg (
dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming
end end
CMD_START: begin CMD_START: begin
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : (|abstractcs_reg[10:8]) ? CMD_DONE : CMD_WAIT; // new command sent to the core // Don't execute the command if cmderror or transfer=0 for abstract register access
dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | dmcontrol_reg[1]; dbg_nxtstate = dmcontrol_reg[1] ? IDLE : ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CMD_WAIT; // new command sent to the core
dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]) | dmcontrol_reg[1];
end end
CMD_WAIT: begin CMD_WAIT: begin
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : CMD_DONE; dbg_nxtstate = dmcontrol_reg[1] ? IDLE : CMD_DONE;
@ -464,7 +478,7 @@ module dbg (
assign dmi_reg_rdata_din[31:0] = ({32{dmi_reg_addr == 7'h4}} & data0_reg[31:0]) | assign dmi_reg_rdata_din[31:0] = ({32{dmi_reg_addr == 7'h4}} & data0_reg[31:0]) |
({32{dmi_reg_addr == 7'h5}} & data1_reg[31:0]) | ({32{dmi_reg_addr == 7'h5}} & data1_reg[31:0]) |
({32{dmi_reg_addr == 7'h10}} & dmcontrol_reg[31:0]) | ({32{dmi_reg_addr == 7'h10}} & {2'b0,dmcontrol_reg[29],1'b0,dmcontrol_reg[27:0]}) | // Read0 to Write only bits
({32{dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0]) | ({32{dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0]) |
({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) | ({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) |
({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) | ({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) |
@ -483,7 +497,7 @@ module dbg (
// interface for the core // interface for the core
assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h2) ? {data1_reg[31:2],2'b0} : {20'b0, command_reg[11:0]}; // Only word addresses for abstract memory assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h2) ? {data1_reg[31:2],2'b0} : {20'b0, command_reg[11:0]}; // Only word addresses for abstract memory
assign dbg_cmd_wrdata[31:0] = data0_reg[31:0]; assign dbg_cmd_wrdata[31:0] = data0_reg[31:0];
assign dbg_cmd_valid = (dbg_state == CMD_START) & ~(|abstractcs_reg[10:8]) & dma_dbg_ready; assign dbg_cmd_valid = (dbg_state == CMD_START) & ~((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) & dma_dbg_ready;
assign dbg_cmd_write = command_reg[16]; assign dbg_cmd_write = command_reg[16];
assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h2) ? 2'b10 : {1'b0, (command_reg[15:12] == 4'b0)}; assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h2) ? 2'b10 : {1'b0, (command_reg[15:12] == 4'b0)};
assign dbg_cmd_size[1:0] = command_reg[21:20]; assign dbg_cmd_size[1:0] = command_reg[21:20];
@ -554,7 +568,7 @@ module dbg (
sb_state_en = 1'b1; sb_state_en = 1'b1;
sbcs_sbbusy_wren = 1'b1; // reset the single read sbcs_sbbusy_wren = 1'b1; // reset the single read
sbcs_sbbusy_din = 1'b0; sbcs_sbbusy_din = 1'b0;
sbaddress0_reg_wren1 = sbcs_reg[16]; // auto increment was set. Update to new address after completing the current command sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b0); // auto increment was set and no error. Update to new address after completing the current command
end end
default : begin default : begin
sb_nxtstate = SBIDLE; sb_nxtstate = SBIDLE;
@ -572,6 +586,9 @@ module dbg (
//rvdff #(.WIDTH(1)) bus_clken_ff (.din(dbg_bus_clk_en), .dout(dbg_bus_clk_en_q), .rst_l(dbg_dm_rst_l), .clk(dbg_sb_c2_free_clk), .*); //rvdff #(.WIDTH(1)) bus_clken_ff (.din(dbg_bus_clk_en), .dout(dbg_bus_clk_en_q), .rst_l(dbg_dm_rst_l), .clk(dbg_sb_c2_free_clk), .*);
rvdff_fpga #(2) axi_bresp_ff (.din(sb_axi_bresp[1:0]), .dout(sb_axi_bresp_q[1:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .clken(bus_clken), .rawclk(clk), .*);
rvdff_fpga #(2) axi_rresp_ff (.din(sb_axi_rresp[1:0]), .dout(sb_axi_rresp_q[1:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .clken(bus_clken), .rawclk(clk), .*);
rvdffs #(.WIDTH(1)) axi_awvalid_ff (.din(sb_axi_awvalid), .dout(sb_axi_awvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*); rvdffs #(.WIDTH(1)) axi_awvalid_ff (.din(sb_axi_awvalid), .dout(sb_axi_awvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
rvdffs #(.WIDTH(1)) axi_awready_ff (.din(sb_axi_awready), .dout(sb_axi_awready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*); rvdffs #(.WIDTH(1)) axi_awready_ff (.din(sb_axi_awready), .dout(sb_axi_awready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
rvdffs #(.WIDTH(1)) axi_wvalid_ff (.din(sb_axi_wvalid), .dout(sb_axi_wvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*); rvdffs #(.WIDTH(1)) axi_wvalid_ff (.din(sb_axi_wvalid), .dout(sb_axi_wvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
@ -581,10 +598,8 @@ module dbg (
rvdffs #(.WIDTH(1)) axi_bvalid_ff (.din(sb_axi_bvalid), .dout(sb_axi_bvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*); rvdffs #(.WIDTH(1)) axi_bvalid_ff (.din(sb_axi_bvalid), .dout(sb_axi_bvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
rvdffs #(.WIDTH(1)) axi_bready_ff (.din(sb_axi_bready), .dout(sb_axi_bready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*); rvdffs #(.WIDTH(1)) axi_bready_ff (.din(sb_axi_bready), .dout(sb_axi_bready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
rvdff #(.WIDTH(2)) axi_bresp_ff (.din(sb_axi_bresp[1:0]), .dout(sb_axi_bresp_q[1:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .*);
rvdffs #(.WIDTH(1)) axi_rvalid_ff (.din(sb_axi_rvalid), .dout(sb_axi_rvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*); rvdffs #(.WIDTH(1)) axi_rvalid_ff (.din(sb_axi_rvalid), .dout(sb_axi_rvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
rvdffs #(.WIDTH(1)) axi_rready_ff (.din(sb_axi_rready), .dout(sb_axi_rready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*); rvdffs #(.WIDTH(1)) axi_rready_ff (.din(sb_axi_rready), .dout(sb_axi_rready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
rvdff #(.WIDTH(2)) axi_rresp_ff (.din(sb_axi_rresp[1:0]), .dout(sb_axi_rresp_q[1:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .*);
rvdffe #(.WIDTH(64)) axi_rdata_ff (.din(sb_axi_rdata[63:0]), .dout(sb_axi_rdata_q[63:0]), .rst_l(dbg_dm_rst_l), .en(bus_clken), .*); rvdffe #(.WIDTH(64)) axi_rdata_ff (.din(sb_axi_rdata[63:0]), .dout(sb_axi_rdata_q[63:0]), .rst_l(dbg_dm_rst_l), .en(bus_clken), .*);
// AXI Request signals // AXI Request signals

2
design/dec/dec_tlu_ctl.sv
View File

@ -2533,7 +2533,7 @@ assign dec_csr_legal_d = ( dec_csr_any_unq_d &
assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) | assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) |
({32{csr_mvendorid}} & 32'h00000045) | ({32{csr_mvendorid}} & 32'h00000045) |
({32{csr_marchid}} & 32'h0000000b) | ({32{csr_marchid}} & 32'h0000000b) |
({32{csr_mimpid}} & 32'h3) | ({32{csr_mimpid}} & 32'h4) |
({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) | ({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) |
({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) | ({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) |
({32{csr_mip}} & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) | ({32{csr_mip}} & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) |

48
design/dma_ctrl.sv
View File

@ -396,9 +396,6 @@ module dma_ctrl (
// Inputs // Inputs
rvdff #(1) ahbs_bus_clken_ff (.din(dma_bus_clk_en), .dout(dma_bus_clk_en_q), .clk(free_clk), .*); rvdff #(1) ahbs_bus_clken_ff (.din(dma_bus_clk_en), .dout(dma_bus_clk_en_q), .clk(free_clk), .*);
rvdff #(1) fifo_full_bus_ff (.din(fifo_full_spec), .dout(fifo_full_spec_bus), .clk(dma_bus_clk), .*);
rvdff #(1) dbg_dma_bubble_ff (.din(dbg_dma_bubble), .dout(dbg_dma_bubble_bus), .clk(dma_bus_clk), .*);
rvdff #(1) dec_tlu_stall_dma_ff (.din(dec_tlu_stall_dma), .dout(dec_tlu_stall_dma_bus), .clk(dma_bus_clk), .*);
rvdff #(1) dma_dbg_cmd_doneff (.din(dma_dbg_cmd_done), .dout(dma_dbg_cmd_done_q), .clk(free_clk), .*); rvdff #(1) dma_dbg_cmd_doneff (.din(dma_dbg_cmd_done), .dout(dma_dbg_cmd_done_q), .clk(free_clk), .*);
// Clock Gating logic // Clock Gating logic
@ -407,7 +404,34 @@ module dma_ctrl (
rvoclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* ); rvoclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* );
rvoclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*); rvoclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*);
rvclkhdr dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*);
`ifndef RV_FPGA_OPTIMIZE
rvclkhdr dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*); // ifndef FPGA_OPTIMIZE
`endif
rvdffsc_fpga #(1) wrbuf_vldff (.din(1'b1), .clear(wrbuf_rst), .dout(wrbuf_vld), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(1) wrbuf_data_vldff(.din(1'b1), .clear(wrbuf_data_rst), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(1) rdbuf_vldff (.din(1'b1), .clear(rdbuf_rst), .dout(rdbuf_vld), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) fifo_full_bus_ff (.din(fifo_full_spec), .dout(fifo_full_spec_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) dbg_dma_bubble_ff (.din(dbg_dma_bubble), .dout(dbg_dma_bubble_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) dec_tlu_stall_dma_ff (.din(dec_tlu_stall_dma), .dout(dec_tlu_stall_dma_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(1) wrbuf_postedff (.din(1'b0), .dout(wrbuf_posted), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(DMA_BUS_TAG) wrbuf_tagff (.din(dma_axi_awid[DMA_BUS_TAG-1:0]), .dout(wrbuf_tag[DMA_BUS_TAG-1:0]), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(3) wrbuf_sizeff (.din(dma_axi_awsize[2:0]), .dout(wrbuf_size[2:0]), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(8) wrbuf_byteenff (.din(dma_axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(DMA_BUS_TAG) rdbuf_tagff (.din(dma_axi_arid[DMA_BUS_TAG-1:0]), .dout(rdbuf_tag[DMA_BUS_TAG-1:0]), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(3) rdbuf_sizeff (.din(dma_axi_arsize[2:0]), .dout(rdbuf_size[2:0]), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(1) mstr_prtyff (.din(axi_mstr_prty_in), .dout(axi_mstr_priority), .en(axi_mstr_prty_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) axi_mstr_validff ( .din(axi_mstr_valid), .dout(axi_mstr_valid_q), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) axi_slv_sentff ( .din(axi_slv_sent), .dout(axi_slv_sent_q), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
rvdffe #(32) wrbuf_addrff(.din(dma_axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & dma_bus_clk_en), .*);
rvdffe #(64) wrbuf_dataff(.din(dma_axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & dma_bus_clk_en), .*);
rvdffe #(32) rdbuf_addrff(.din(dma_axi_araddr[31:0]), .dout(rdbuf_addr[31:0]), .en(rdbuf_en & dma_bus_clk_en), .*);
// Write channel buffer // Write channel buffer
assign wrbuf_en = dma_axi_awvalid & dma_axi_awready; assign wrbuf_en = dma_axi_awvalid & dma_axi_awready;
@ -416,23 +440,11 @@ module dma_ctrl (
assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en; assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en;
assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en; assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en;
rvdffsc #(.WIDTH(1)) wrbuf_vldff(.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(dma_bus_clk), .*);
rvdffsc #(.WIDTH(1)) wrbuf_data_vldff(.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_data_rst), .clk(dma_bus_clk), .*);
rvdffs #(.WIDTH(1)) wrbuf_postedff(.din(1'b0), .dout(wrbuf_posted), .en(wrbuf_en), .clk(dma_bus_clk), .*);
rvdffs #(.WIDTH(DMA_BUS_TAG)) wrbuf_tagff(.din(dma_axi_awid[DMA_BUS_TAG-1:0]), .dout(wrbuf_tag[DMA_BUS_TAG-1:0]), .en(wrbuf_en), .clk(dma_bus_clk), .*);
rvdffs #(.WIDTH(3)) wrbuf_sizeff(.din(dma_axi_awsize[2:0]), .dout(wrbuf_size[2:0]), .en(wrbuf_en), .clk(dma_bus_clk), .*);
rvdffe #(.WIDTH(32)) wrbuf_addrff(.din(dma_axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & dma_bus_clk_en), .*);
rvdffe #(.WIDTH(64)) wrbuf_dataff(.din(dma_axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & dma_bus_clk_en), .*);
rvdffs #(.WIDTH(8)) wrbuf_byteenff(.din(dma_axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(dma_bus_clk), .*);
// Read channel buffer // Read channel buffer
assign rdbuf_en = dma_axi_arvalid & dma_axi_arready; assign rdbuf_en = dma_axi_arvalid & dma_axi_arready;
assign rdbuf_cmd_sent = axi_mstr_valid & ~axi_mstr_write & dma_fifo_ready; assign rdbuf_cmd_sent = axi_mstr_valid & ~axi_mstr_write & dma_fifo_ready;
assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en; assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en;
rvdffsc #(.WIDTH(1)) rdbuf_vldff(.din(1'b1), .dout(rdbuf_vld), .en(rdbuf_en), .clear(rdbuf_rst), .clk(dma_bus_clk), .*);
rvdffs #(.WIDTH(DMA_BUS_TAG)) rdbuf_tagff(.din(dma_axi_arid[DMA_BUS_TAG-1:0]), .dout(rdbuf_tag[DMA_BUS_TAG-1:0]), .en(rdbuf_en), .clk(dma_bus_clk), .*);
rvdffs #(.WIDTH(3)) rdbuf_sizeff(.din(dma_axi_arsize[2:0]), .dout(rdbuf_size[2:0]), .en(rdbuf_en), .clk(dma_bus_clk), .*);
rvdffe #(.WIDTH(32)) rdbuf_addrff(.din(dma_axi_araddr[31:0]), .dout(rdbuf_addr[31:0]), .en(rdbuf_en & dma_bus_clk_en), .*);
assign dma_axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent); assign dma_axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent);
assign dma_axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent); assign dma_axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent);
@ -452,10 +464,6 @@ module dma_ctrl (
assign axi_mstr_sel = (wrbuf_vld & wrbuf_data_vld & rdbuf_vld) ? axi_mstr_priority : (wrbuf_vld & wrbuf_data_vld); assign axi_mstr_sel = (wrbuf_vld & wrbuf_data_vld & rdbuf_vld) ? axi_mstr_priority : (wrbuf_vld & wrbuf_data_vld);
assign axi_mstr_prty_in = ~axi_mstr_priority; assign axi_mstr_prty_in = ~axi_mstr_priority;
assign axi_mstr_prty_en = axi_mstr_valid; assign axi_mstr_prty_en = axi_mstr_valid;
rvdffs #(.WIDTH(1)) mstr_prtyff(.din(axi_mstr_prty_in), .dout(axi_mstr_priority), .en(axi_mstr_prty_en), .clk(dma_bus_clk), .*);
rvdff #(.WIDTH(1)) axi_mstr_validff (.din(axi_mstr_valid), .dout(axi_mstr_valid_q), .clk(dma_bus_clk), .*);
rvdff #(.WIDTH(1)) axi_slv_sentff (.din(axi_slv_sent), .dout(axi_slv_sent_q), .clk(dma_bus_clk), .*);
//assign axi_slv_valid = fifo_valid[RspPtr] & ~fifo_rsp_done[RspPtr] & ~fifo_dbg[RspPtr] & //assign axi_slv_valid = fifo_valid[RspPtr] & ~fifo_rsp_done[RspPtr] & ~fifo_dbg[RspPtr] &
// ((fifo_write[RspPtr] & fifo_done_bus[RspPtr]) | (~fifo_write[RspPtr] & fifo_data_bus_valid[RspPtr]) | fifo_error_bus[RspPtr]); // ((fifo_write[RspPtr] & fifo_done_bus[RspPtr]) | (~fifo_write[RspPtr] & fifo_data_bus_valid[RspPtr]) | fifo_error_bus[RspPtr]);

24
design/exu/exu_mul_ctl.sv
View File

@ -59,20 +59,23 @@ module exu_mul_ctl
assign mul_c1_e2_clken = (valid_e1 | clk_override) & ~freeze; assign mul_c1_e2_clken = (valid_e1 | clk_override) & ~freeze;
assign mul_c1_e3_clken = (valid_e2 | clk_override) & ~freeze; assign mul_c1_e3_clken = (valid_e2 | clk_override) & ~freeze;
`ifndef RV_FPGA_OPTIMIZE
// C1 - 1 clock pulse for data // C1 - 1 clock pulse for data
rvclkhdr exu_mul_c1e1_cgc (.*, .en(mul_c1_e1_clken), .l1clk(exu_mul_c1_e1_clk)); rvclkhdr exu_mul_c1e1_cgc (.*, .en(mul_c1_e1_clken), .l1clk(exu_mul_c1_e1_clk)); // ifndef FPGA_OPTIMIZE
rvclkhdr exu_mul_c1e2_cgc (.*, .en(mul_c1_e2_clken), .l1clk(exu_mul_c1_e2_clk)); rvclkhdr exu_mul_c1e2_cgc (.*, .en(mul_c1_e2_clken), .l1clk(exu_mul_c1_e2_clk)); // ifndef FPGA_OPTIMIZE
rvclkhdr exu_mul_c1e3_cgc (.*, .en(mul_c1_e3_clken), .l1clk(exu_mul_c1_e3_clk)); rvclkhdr exu_mul_c1e3_cgc (.*, .en(mul_c1_e3_clken), .l1clk(exu_mul_c1_e3_clk)); // ifndef FPGA_OPTIMIZE
`endif
// --------------------------- Input flops ---------------------------------- // --------------------------- Input flops ----------------------------------
rvdffs #(1) valid_e1_ff (.*, .din(mp.valid), .dout(valid_e1), .clk(active_clk), .en(~freeze)); rvdffs #(1) valid_e1_ff (.*, .din(mp.valid), .dout(valid_e1), .clk(active_clk), .en(~freeze));
rvdff #(1) rs1_sign_e1_ff (.*, .din(mp.rs1_sign), .dout(rs1_sign_e1), .clk(exu_mul_c1_e1_clk));
rvdff #(1) rs2_sign_e1_ff (.*, .din(mp.rs2_sign), .dout(rs2_sign_e1), .clk(exu_mul_c1_e1_clk)); rvdff_fpga #(1) rs1_sign_e1_ff (.*, .din(mp.rs1_sign), .dout(rs1_sign_e1), .clk(exu_mul_c1_e1_clk), .clken(mul_c1_e1_clken), .rawclk(clk));
rvdff #(1) low_e1_ff (.*, .din(mp.low), .dout(low_e1), .clk(exu_mul_c1_e1_clk)); rvdff_fpga #(1) rs2_sign_e1_ff (.*, .din(mp.rs2_sign), .dout(rs2_sign_e1), .clk(exu_mul_c1_e1_clk), .clken(mul_c1_e1_clken), .rawclk(clk));
rvdff #(1) ld_rs1_byp_e1_ff (.*, .din(mp.load_mul_rs1_bypass_e1), .dout(load_mul_rs1_bypass_e1), .clk(exu_mul_c1_e1_clk)); rvdff_fpga #(1) low_e1_ff (.*, .din(mp.low), .dout(low_e1), .clk(exu_mul_c1_e1_clk), .clken(mul_c1_e1_clken), .rawclk(clk));
rvdff #(1) ld_rs2_byp_e1_ff (.*, .din(mp.load_mul_rs2_bypass_e1), .dout(load_mul_rs2_bypass_e1), .clk(exu_mul_c1_e1_clk)); rvdff_fpga #(1) ld_rs1_byp_e1_ff (.*, .din(mp.load_mul_rs1_bypass_e1), .dout(load_mul_rs1_bypass_e1), .clk(exu_mul_c1_e1_clk), .clken(mul_c1_e1_clken), .rawclk(clk));
rvdff_fpga #(1) ld_rs2_byp_e1_ff (.*, .din(mp.load_mul_rs2_bypass_e1), .dout(load_mul_rs2_bypass_e1), .clk(exu_mul_c1_e1_clk), .clken(mul_c1_e1_clken), .rawclk(clk));
rvdffe #(32) a_e1_ff (.*, .din(a[31:0]), .dout(a_ff_e1[31:0]), .en(mul_c1_e1_clken)); rvdffe #(32) a_e1_ff (.*, .din(a[31:0]), .dout(a_ff_e1[31:0]), .en(mul_c1_e1_clken));
rvdffe #(32) b_e1_ff (.*, .din(b[31:0]), .dout(b_ff_e1[31:0]), .en(mul_c1_e1_clken)); rvdffe #(32) b_e1_ff (.*, .din(b[31:0]), .dout(b_ff_e1[31:0]), .en(mul_c1_e1_clken));
@ -89,7 +92,8 @@ module exu_mul_ctl
rvdffs #(1) valid_e2_ff (.*, .din(valid_e1), .dout(valid_e2), .clk(active_clk), .en(~freeze)); rvdffs #(1) valid_e2_ff (.*, .din(valid_e1), .dout(valid_e2), .clk(active_clk), .en(~freeze));
rvdff #(1) low_e2_ff (.*, .din(low_e1), .dout(low_e2), .clk(exu_mul_c1_e2_clk));
rvdff_fpga #(1) low_e2_ff (.*, .din(low_e1), .dout(low_e2), .clk(exu_mul_c1_e2_clk), .clken(mul_c1_e2_clken), .rawclk(clk));
rvdffe #(33) a_e2_ff (.*, .din({rs1_neg_e1, a_e1[31:0]}), .dout(a_ff_e2[32:0]), .en(mul_c1_e2_clken)); rvdffe #(33) a_e2_ff (.*, .din({rs1_neg_e1, a_e1[31:0]}), .dout(a_ff_e2[32:0]), .en(mul_c1_e2_clken));
rvdffe #(33) b_e2_ff (.*, .din({rs2_neg_e1, b_e1[31:0]}), .dout(b_ff_e2[32:0]), .en(mul_c1_e2_clken)); rvdffe #(33) b_e2_ff (.*, .din({rs2_neg_e1, b_e1[31:0]}), .dout(b_ff_e2[32:0]), .en(mul_c1_e2_clken));
@ -103,8 +107,8 @@ module exu_mul_ctl
assign prod_e2[65:0] = a_ff_e2 * b_ff_e2; assign prod_e2[65:0] = a_ff_e2 * b_ff_e2;
rvdff_fpga #(1) low_e3_ff (.*, .din(low_e2), .dout(low_e3), .clk(exu_mul_c1_e3_clk), .clken(mul_c1_e3_clken), .rawclk(clk));
rvdff #(1) low_e3_ff (.*, .din(low_e2), .dout(low_e3), .clk(exu_mul_c1_e3_clk));
rvdffe #(64) prod_e3_ff (.*, .din(prod_e2[63:0]), .dout(prod_e3[63:0]), .en(mul_c1_e3_clken)); rvdffe #(64) prod_e3_ff (.*, .din(prod_e2[63:0]), .dout(prod_e3[63:0]), .en(mul_c1_e3_clken));

4
design/ifu/ifu.sv
View File

@ -123,7 +123,7 @@ module ifu
output logic ifu_pmu_fetch_stall, output logic ifu_pmu_fetch_stall,
// I$ & ITAG Ports // I$ & ITAG Ports
output logic [31:3] ic_rw_addr, // Read/Write addresss to the Icache. output logic [31:2] ic_rw_addr, // Read/Write addresss to the Icache.
output logic [3:0] ic_wr_en, // Icache write enable, when filling the Icache. output logic [3:0] ic_wr_en, // Icache write enable, when filling the Icache.
output logic ic_rd_en, // Icache read enable. output logic ic_rd_en, // Icache read enable.
`ifdef RV_ICACHE_ECC `ifdef RV_ICACHE_ECC
@ -358,7 +358,7 @@ module ifu
assign mppc_ns[31:1] = `EXU.exu_i0_flush_upper_e1 ? `DEC.decode.i0_pc_e1[31:1] : (`EXU.exu_i1_flush_upper_e1 ? `DEC.decode.i1_pc_e1[31:1] : (`EXU.exu_i0_flush_lower_e4 ? `DEC.decode.i0_pc_e4[31:1] : `DEC.decode.i1_pc_e4[31:1])); assign mppc_ns[31:1] = `EXU.exu_i0_flush_upper_e1 ? `DEC.decode.i0_pc_e1[31:1] : (`EXU.exu_i1_flush_upper_e1 ? `DEC.decode.i1_pc_e1[31:1] : (`EXU.exu_i0_flush_lower_e4 ? `DEC.decode.i0_pc_e4[31:1] : `DEC.decode.i1_pc_e4[31:1]));
assign mppc_ns[0] = 1'b0; assign mppc_ns[0] = 1'b0;
logic [3:0] ic_rd_hit_f2; logic [3:0] ic_rd_hit_f2;
rvdff #(36) mdseal_ff (.*, .din({mppc_ns[31:0], mem_ctl.ic_rd_hit[3:0]}), .dout({mppc[31:0],ic_rd_hit_f2[3:0]})); rvdff #(36) junk_ff (.*, .clk(free_clk), .din({mppc_ns[31:0], mem_ctl.ic_rd_hit[3:0]}), .dout({mppc[31:0],ic_rd_hit_f2[3:0]}));
logic [2:0] tmp_bnk; logic [2:0] tmp_bnk;
assign tmp_bnk[2:0] = encode8_3(bp.btb_sel_f2[7:0]); assign tmp_bnk[2:0] = encode8_3(bp.btb_sel_f2[7:0]);
always @(negedge clk) begin always @(negedge clk) begin

15
design/ifu/ifu_bp_ctl.sv
View File

@ -1289,7 +1289,7 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2]
({31{e1_rs_hold}} & e1_rets_out[i][31:1]) ); ({31{e1_rs_hold}} & e1_rets_out[i][31:1]) );
rvdff #(31) e1_rets_ff (.*, .din(e1_rets_in[i][31:1]), .dout(e1_rets_out[i][31:1])); rvdffe #(31) e1_rets_ff (.*, .en(~e1_rs_hold), .din(e1_rets_in[i][31:1]), .dout(e1_rets_out[i][31:1]));
end : e1_retstack end : e1_retstack
@ -1346,7 +1346,7 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2]
({31{e4_rs_hold}} & e4_rets_out[i][31:1]) ); ({31{e4_rs_hold}} & e4_rets_out[i][31:1]) );
rvdff #(31) e4_rets_ff (.*, .din(e4_rets_in[i][31:1]), .dout(e4_rets_out[i][31:1])); rvdffe #(31) e4_rets_ff (.*, .en(~e4_rs_hold), .din(e4_rets_in[i][31:1]), .dout(e4_rets_out[i][31:1]));
end : e4_retstack end : e4_retstack
@ -1628,7 +1628,11 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2]
(bht_wr_en1[i] & ((bht_wr_addr1[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) | (bht_wr_en1[i] & ((bht_wr_addr1[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
(bht_wr_en2[i] & ((bht_wr_addr2[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)); (bht_wr_en2[i] & ((bht_wr_addr2[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH));
rvclkhdr bht_bank_grp_cgc ( .en(bht_bank_clken[i][k]), .l1clk(bht_bank_clk[i][k]), .* ); `ifndef RV_FPGA_OPTIMIZE
rvclkhdr bht_bank_grp_cgc ( .en(bht_bank_clken[i][k]), .l1clk(bht_bank_clk[i][k]), .* ); // ifndef RV_FPGA_OPTIMIZE
`else
assign bht_bank_clk[i][k] = '0;
`endif
for (j=0 ; j<NUM_BHT_LOOP ; j++) begin : BHT_FLOPS for (j=0 ; j<NUM_BHT_LOOP ; j++) begin : BHT_FLOPS
assign bht_bank_sel[i][k][j] = (bht_wr_en0[i] & (bht_wr_addr0[NUM_BHT_LOOP_INNER_HI :`RV_BHT_ADDR_LO] == j) & ((bht_wr_addr0[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) | assign bht_bank_sel[i][k][j] = (bht_wr_en0[i] & (bht_wr_addr0[NUM_BHT_LOOP_INNER_HI :`RV_BHT_ADDR_LO] == j) & ((bht_wr_addr0[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
@ -1639,9 +1643,10 @@ assign fgmask_f2[0] = (~ifc_fetch_addr_f2[3] & ~ifc_fetch_addr_f2[2]
(bht_wr_en1[i] & (bht_wr_addr1[NUM_BHT_LOOP_INNER_HI:`RV_BHT_ADDR_LO] == j) & ((bht_wr_addr1[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ? bht_wr_data1[1:0] : (bht_wr_en1[i] & (bht_wr_addr1[NUM_BHT_LOOP_INNER_HI:`RV_BHT_ADDR_LO] == j) & ((bht_wr_addr1[`RV_BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ? bht_wr_data1[1:0] :
bht_wr_data0[1:0] ; bht_wr_data0[1:0] ;
rvdffs_fpga #(2) bht_bank (.*,
rvdffs #(2) bht_bank (.*,
.clk (bht_bank_clk[i][k]), .clk (bht_bank_clk[i][k]),
.clken (bht_bank_sel[i][k][j]),
.rawclk (clk),
.en (bht_bank_sel[i][k][j]), .en (bht_bank_sel[i][k][j]),
.din (bht_bank_wr_data[i][k][j]), .din (bht_bank_wr_data[i][k][j]),
.dout (bht_bank_rd_data_out[i][(16*k)+j])); .dout (bht_bank_rd_data_out[i][(16*k)+j]));

65
design/ifu/ifu_ic_mem.sv
View File

@ -19,12 +19,13 @@
///////////////////////////////////////////////////// /////////////////////////////////////////////////////
module ifu_ic_mem module ifu_ic_mem
( (
input logic free_clk,
input logic clk, input logic clk,
input logic rst_l, input logic rst_l,
input logic clk_override, input logic clk_override,
input logic dec_tlu_core_ecc_disable, input logic dec_tlu_core_ecc_disable,
input logic [31:3] ic_rw_addr, input logic [31:2] ic_rw_addr,
input logic [3:0] ic_wr_en , // Which way to write input logic [3:0] ic_wr_en , // Which way to write
input logic ic_rd_en , // Read enable input logic ic_rd_en , // Read enable
@ -79,7 +80,7 @@ module ifu_ic_mem
.*, .*,
.ic_wr_en (ic_wr_en[3:0]), .ic_wr_en (ic_wr_en[3:0]),
.ic_debug_addr(ic_debug_addr[ICACHE_TAG_HIGH-1:2]), .ic_debug_addr(ic_debug_addr[ICACHE_TAG_HIGH-1:2]),
.ic_rw_addr (ic_rw_addr[ICACHE_TAG_HIGH-1:3]) .ic_rw_addr (ic_rw_addr[ICACHE_TAG_HIGH-1:2])
) ; ) ;
endmodule endmodule
@ -93,11 +94,12 @@ module IC_DATA #(parameter ICACHE_TAG_HIGH = 16 ,
ICACHE_IC_DEPTH=1024 ICACHE_IC_DEPTH=1024
) )
( (
input logic free_clk,
input logic clk, input logic clk,
input logic rst_l, input logic rst_l,
input logic clk_override, input logic clk_override,
input logic [ICACHE_TAG_HIGH-1:3] ic_rw_addr, input logic [ICACHE_TAG_HIGH-1:2] ic_rw_addr,
input logic [3:0] ic_wr_en, input logic [3:0] ic_wr_en,
input logic ic_rd_en, // Read enable input logic ic_rd_en, // Read enable
`ifdef RV_ICACHE_ECC `ifdef RV_ICACHE_ECC
@ -128,7 +130,7 @@ module IC_DATA #(parameter ICACHE_TAG_HIGH = 16 ,
logic [5:4] ic_rw_addr_ff; logic [5:4] ic_rw_addr_ff;
logic [3:0][3:0] ic_b_sb_wren; // way, bank logic [3:0][3:0] ic_b_sb_wren, ic_bank_way_clken, ic_bank_way_clk; // way, bank
logic ic_debug_sel_sb0 ; logic ic_debug_sel_sb0 ;
logic ic_debug_sel_sb1 ; logic ic_debug_sel_sb1 ;
@ -146,8 +148,6 @@ module IC_DATA #(parameter ICACHE_TAG_HIGH = 16 ,
logic [3:0] [33:0] ic_sb_wr_data; logic [3:0] [33:0] ic_sb_wr_data;
`endif `endif
logic [3:0] ic_bank_way_clken; // bank , way
logic [3:0] ic_bank_way_clk ; // bank , way
logic ic_b_rden; logic ic_b_rden;
logic [3:0] ic_debug_rd_way_en; // debug wr_way logic [3:0] ic_debug_rd_way_en; // debug wr_way
logic [3:0] ic_debug_rd_way_en_ff; // debug wr_way logic [3:0] ic_debug_rd_way_en_ff; // debug wr_way
@ -197,13 +197,12 @@ module IC_DATA #(parameter ICACHE_TAG_HIGH = 16 ,
assign ic_b_rden = (ic_rd_en | ic_debug_rd_en ); assign ic_b_rden = (ic_rd_en | ic_debug_rd_en );
assign ic_bank_way_clken[3:0] = ({4{ic_b_rden | clk_override }}) | logic [3:0] ic_bank_read;
ic_b_sb_wren[0][3:0] | logic [3:0] ic_bank_read_ff;
ic_b_sb_wren[1][3:0] | assign ic_bank_read[0] = (ic_b_rden) & (~|ic_rw_addr[3:2] | ic_debug_rd_en);
ic_b_sb_wren[2][3:0] | assign ic_bank_read[1] = (ic_b_rden) & (~ic_rw_addr[3] | ic_debug_rd_en);
ic_b_sb_wren[3][3:0] ; assign ic_bank_read[2] = (ic_b_rden) & (~&ic_rw_addr[3:2] | ic_debug_rd_en);
assign ic_bank_read[3] = (ic_b_rden) | ic_debug_rd_en;
assign ic_rw_addr_q[ICACHE_TAG_HIGH-1:4] = (ic_debug_rd_en | ic_debug_wr_en) ? assign ic_rw_addr_q[ICACHE_TAG_HIGH-1:4] = (ic_debug_rd_en | ic_debug_wr_en) ?
ic_debug_addr[ICACHE_TAG_HIGH-1:4] : ic_debug_addr[ICACHE_TAG_HIGH-1:4] :
@ -212,10 +211,17 @@ module IC_DATA #(parameter ICACHE_TAG_HIGH = 16 ,
logic ic_debug_rd_en_ff; logic ic_debug_rd_en_ff;
rvdff #(2) adr_ff (.*, rvdff #(2) adr_ff (.*,
.clk(free_clk),
.din ({ic_rw_addr_q[5:4]}), .din ({ic_rw_addr_q[5:4]}),
.dout({ic_rw_addr_ff[5:4]})); .dout({ic_rw_addr_ff[5:4]}));
rvdff #(4) bank_adr_ff (.*,
.clk(free_clk),
.din (ic_bank_read[3:0]),
.dout(ic_bank_read_ff[3:0]));
rvdff #(5) debug_rd_wy_ff (.*, rvdff #(5) debug_rd_wy_ff (.*,
.clk(free_clk),
.din ({ic_debug_rd_way_en[3:0], ic_debug_rd_en}), .din ({ic_debug_rd_way_en[3:0], ic_debug_rd_en}),
.dout({ic_debug_rd_way_en_ff[3:0], ic_debug_rd_en_ff})); .dout({ic_debug_rd_way_en_ff[3:0], ic_debug_rd_en_ff}));
@ -225,13 +231,17 @@ localparam NUM_SUBBANKS=4 ;
for (genvar i=0; i<NUM_WAYS; i++) begin: WAYS for (genvar i=0; i<NUM_WAYS; i++) begin: WAYS
rvoclkhdr bank_way_c1_cgc ( .en(ic_bank_way_clken[i]), .l1clk(ic_bank_way_clk[i]), .* );
for (genvar k=0; k<NUM_SUBBANKS; k++) begin: SUBBANKS // 16B subbank for (genvar k=0; k<NUM_SUBBANKS; k++) begin: SUBBANKS // 16B subbank
// way3-bank3, way3-bank2, ... way0-bank0
assign ic_bank_way_clken[i][k] = ic_bank_read[k] | ic_b_sb_wren[k][i];
rvoclkhdr bank_way_bank_c1_cgc ( .en(ic_bank_way_clken[i][k] | clk_override), .l1clk(ic_bank_way_clk[i][k]), .* );
`ifdef RV_ICACHE_ECC `ifdef RV_ICACHE_ECC
`RV_ICACHE_DATA_CELL ic_bank_sb_way_data ( `RV_ICACHE_DATA_CELL ic_bank_sb_way_data (
.CLK(ic_bank_way_clk[i]), .CLK(ic_bank_way_clk[i][k]),
.WE (ic_b_sb_wren[k][i]), .WE (ic_b_sb_wren[k][i]),
.D (ic_sb_wr_data[k][41:0]), .D (ic_sb_wr_data[k][41:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]), .ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]),
@ -239,7 +249,7 @@ localparam NUM_SUBBANKS=4 ;
); );
`else `else
`RV_ICACHE_DATA_CELL ic_bank_sb_way_data ( `RV_ICACHE_DATA_CELL ic_bank_sb_way_data (
.CLK(ic_bank_way_clk[i]), .CLK(ic_bank_way_clk[i][k]),
.WE (ic_b_sb_wren[k][i]), .WE (ic_b_sb_wren[k][i]),
.D (ic_sb_wr_data[k][33:0]), .D (ic_sb_wr_data[k][33:0]),
.ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]), .ADR(ic_rw_addr_q[ICACHE_TAG_HIGH-1:4]),
@ -261,10 +271,10 @@ localparam NUM_SUBBANKS=4 ;
logic [3:0] [167:0] wb_dout_way_with_premux; logic [3:0] [167:0] wb_dout_way_with_premux;
assign ic_premux_data_ext[167:0] = {10'b0,ic_premux_data[127:96],10'b0,ic_premux_data[95:64] ,10'b0,ic_premux_data[63:32],10'b0,ic_premux_data[31:0]}; assign ic_premux_data_ext[167:0] = {10'b0,ic_premux_data[127:96],10'b0,ic_premux_data[95:64] ,10'b0,ic_premux_data[63:32],10'b0,ic_premux_data[31:0]};
assign wb_dout_way[0][167:0] = wb_dout[0][167:0]; assign wb_dout_way[0][167:0] = wb_dout[0][167:0] & { {42{ic_bank_read_ff[3]}} , {42{ic_bank_read_ff[2]}} , {42{ic_bank_read_ff[1]}} , {42{ic_bank_read_ff[0]}} };
assign wb_dout_way[1][167:0] = wb_dout[1][167:0]; assign wb_dout_way[1][167:0] = wb_dout[1][167:0] & { {42{ic_bank_read_ff[3]}} , {42{ic_bank_read_ff[2]}} , {42{ic_bank_read_ff[1]}} , {42{ic_bank_read_ff[0]}} };
assign wb_dout_way[2][167:0] = wb_dout[2][167:0]; assign wb_dout_way[2][167:0] = wb_dout[2][167:0] & { {42{ic_bank_read_ff[3]}} , {42{ic_bank_read_ff[2]}} , {42{ic_bank_read_ff[1]}} , {42{ic_bank_read_ff[0]}} };
assign wb_dout_way[3][167:0] = wb_dout[3][167:0]; assign wb_dout_way[3][167:0] = wb_dout[3][167:0] & { {42{ic_bank_read_ff[3]}} , {42{ic_bank_read_ff[2]}} , {42{ic_bank_read_ff[1]}} , {42{ic_bank_read_ff[0]}} };
assign wb_dout_way_with_premux[0][167:0] = ic_sel_premux_data ? ic_premux_data_ext[167:0] : wb_dout_way[0][167:0] ; assign wb_dout_way_with_premux[0][167:0] = ic_sel_premux_data ? ic_premux_data_ext[167:0] : wb_dout_way[0][167:0] ;
@ -283,10 +293,10 @@ localparam NUM_SUBBANKS=4 ;
logic [3:0] [135:0] wb_dout_way_with_premux; logic [3:0] [135:0] wb_dout_way_with_premux;
assign ic_premux_data_ext[135:0] = {2'b0,ic_premux_data[127:96],2'b0,ic_premux_data[95:64] ,2'b0,ic_premux_data[63:32],2'b0,ic_premux_data[31:0]}; assign ic_premux_data_ext[135:0] = {2'b0,ic_premux_data[127:96],2'b0,ic_premux_data[95:64] ,2'b0,ic_premux_data[63:32],2'b0,ic_premux_data[31:0]};
assign wb_dout_way[0][135:0] = wb_dout[0][135:0]; assign wb_dout_way[0][135:0] = wb_dout[0][135:0] & { {34{ic_bank_read_ff[3]}} , {34{ic_bank_read_ff[2]}} , {34{ic_bank_read_ff[1]}} , {34{ic_bank_read_ff[0]}} };
assign wb_dout_way[1][135:0] = wb_dout[1][135:0]; assign wb_dout_way[1][135:0] = wb_dout[1][135:0] & { {34{ic_bank_read_ff[3]}} , {34{ic_bank_read_ff[2]}} , {34{ic_bank_read_ff[1]}} , {34{ic_bank_read_ff[0]}} };
assign wb_dout_way[2][135:0] = wb_dout[2][135:0]; assign wb_dout_way[2][135:0] = wb_dout[2][135:0] & { {34{ic_bank_read_ff[3]}} , {34{ic_bank_read_ff[2]}} , {34{ic_bank_read_ff[1]}} , {34{ic_bank_read_ff[0]}} };
assign wb_dout_way[3][135:0] = wb_dout[3][135:0]; assign wb_dout_way[3][135:0] = wb_dout[3][135:0] & { {34{ic_bank_read_ff[3]}} , {34{ic_bank_read_ff[2]}} , {34{ic_bank_read_ff[1]}} , {34{ic_bank_read_ff[0]}} };
assign wb_dout_way_with_premux[0][135:0] = ic_sel_premux_data ? ic_premux_data_ext[135:0] : wb_dout_way[0][135:0] ; assign wb_dout_way_with_premux[0][135:0] = ic_sel_premux_data ? ic_premux_data_ext[135:0] : wb_dout_way[0][135:0] ;
assign wb_dout_way_with_premux[1][135:0] = ic_sel_premux_data ? ic_premux_data_ext[135:0] : wb_dout_way[1][135:0] ; assign wb_dout_way_with_premux[1][135:0] = ic_sel_premux_data ? ic_premux_data_ext[135:0] : wb_dout_way[1][135:0] ;
@ -311,6 +321,7 @@ module IC_TAG #(parameter ICACHE_TAG_HIGH = 16 ,
ICACHE_TAG_DEPTH=1024 ICACHE_TAG_DEPTH=1024
) )
( (
input logic free_clk,
input logic clk, input logic clk,
input logic rst_l, input logic rst_l,
input logic clk_override, input logic clk_override,
@ -374,6 +385,7 @@ module IC_TAG #(parameter ICACHE_TAG_HIGH = 16 ,
assign ic_tag_clken[3:0] = {4{ic_rd_en | clk_override}} | ic_wr_en[3:0] | ic_debug_wr_way_en[3:0] | ic_debug_rd_way_en[3:0]; assign ic_tag_clken[3:0] = {4{ic_rd_en | clk_override}} | ic_wr_en[3:0] | ic_debug_wr_way_en[3:0] | ic_debug_rd_way_en[3:0];
rvdff #(32-ICACHE_TAG_HIGH) adr_ff (.*, rvdff #(32-ICACHE_TAG_HIGH) adr_ff (.*,
.clk(free_clk),
.din ({ic_rw_addr[31:ICACHE_TAG_HIGH]}), .din ({ic_rw_addr[31:ICACHE_TAG_HIGH]}),
.dout({ic_rw_addr_ff[31:ICACHE_TAG_HIGH]})); .dout({ic_rw_addr_ff[31:ICACHE_TAG_HIGH]}));
@ -436,6 +448,7 @@ end
rvdff #(4) tag_rd_wy_ff (.*, rvdff #(4) tag_rd_wy_ff (.*,
.clk(free_clk),
.din ({ic_debug_rd_way_en[3:0]}), .din ({ic_debug_rd_way_en[3:0]}),
.dout({ic_debug_rd_way_en_ff[3:0]})); .dout({ic_debug_rd_way_en_ff[3:0]}));
@ -443,7 +456,9 @@ end
for (genvar i=0; i<NUM_WAYS; i++) begin: WAYS for (genvar i=0; i<NUM_WAYS; i++) begin: WAYS
rvclkhdr ic_tag_c1_cgc ( .en(ic_tag_clken[i]), .l1clk(ic_tag_clk[i]), .* );
rvoclkhdr ic_tag_c1_cgc ( .en(ic_tag_clken[i]), .l1clk(ic_tag_clk[i]), .* );
if (ICACHE_TAG_DEPTH == 64 ) begin : ICACHE_SZ_16 if (ICACHE_TAG_DEPTH == 64 ) begin : ICACHE_SZ_16
`ifdef RV_ICACHE_ECC `ifdef RV_ICACHE_ECC
ram_64x25 ic_way_tag ( ram_64x25 ic_way_tag (

3
design/ifu/ifu_iccm_mem.sv
View File

@ -24,6 +24,7 @@ module ifu_iccm_mem
( (
input logic clk, input logic clk,
input logic free_clk,
input logic rst_l, input logic rst_l,
input logic clk_override, input logic clk_override,
@ -136,7 +137,7 @@ module ifu_iccm_mem
end end
// 8 banks, each bank 8B, we index as 4 banks // 8 banks, each bank 8B, we index as 4 banks
else begin else begin
rvdff #(2) rd_addr_ff (.*, .din(iccm_rw_addr[5:4]), .dout(iccm_rw_addr_q[5:4]) ); rvdff #(2) rd_addr_ff (.*, .clk(free_clk), .din(iccm_rw_addr[5:4]), .dout(iccm_rw_addr_q[5:4]) );
end end
endmodule // ifu_iccm_mem endmodule // ifu_iccm_mem

106
design/ifu/ifu_mem_ctl.sv
View File

@ -122,7 +122,7 @@ module ifu_mem_ctl
// I$ & ITAG Ports // I$ & ITAG Ports
output logic [31:3] ic_rw_addr, // Read/Write addresss to the Icache. output logic [31:2] ic_rw_addr, // Read/Write addresss to the Icache.
output logic [3:0] ic_wr_en, // Icache write enable, when filling the Icache. output logic [3:0] ic_wr_en, // Icache write enable, when filling the Icache.
output logic ic_rd_en, // Icache read enable. output logic ic_rd_en, // Icache read enable.
@ -377,8 +377,7 @@ module ifu_mem_ctl
assign debug_c1_clken = ic_debug_rd_en | ic_debug_wr_en ; assign debug_c1_clken = ic_debug_rd_en | ic_debug_wr_en ;
// C1 - 1 clock pulse for data // C1 - 1 clock pulse for data
rvclkhdr fetch_f1_f2_c1_cgc ( .en(fetch_f1_f2_c1_clken), .l1clk(fetch_f1_f2_c1_clk), .* );
rvclkhdr debug_c1_cgc ( .en(debug_c1_clken), .l1clk(debug_c1_clk), .* );
// ------ end clock gating section ------------------------ // ------ end clock gating section ------------------------
@ -501,20 +500,20 @@ module ifu_mem_ctl
assign vaddr_f2[3:1] = ifu_fetch_addr_int_f2[3:1] ; assign vaddr_f2[3:1] = ifu_fetch_addr_int_f2[3:1] ;
rvdff #(1) unc_miss_ff (.*, .clk(fetch_f1_f2_c1_clk), .din (uncacheable_miss_in), .dout(uncacheable_miss_ff));
rvdffe #(31) imb_f2_ff (.*, .en(fetch_f1_f2_c1_clken), .din ({imb_in[31:1]}), .dout({imb_ff[31:1]}));
rvdff #(3) mb_rep_wayf2_ff (.*, .clk(fetch_f1_f2_c1_clk), .din ({way_status_mb_in[2:0]}), .dout({way_status_mb_ff[2:0]}));
rvdff #(4) mb_tagv_ff (.*, .clk(fetch_f1_f2_c1_clk), .din ({tagv_mb_in[3:0]}), .dout({tagv_mb_ff[3:0]})); rvdff_fpga #(1) unc_miss_ff (.*, .clk(fetch_f1_f2_c1_clk), .clken(fetch_f1_f2_c1_clken), .rawclk(clk), .din (uncacheable_miss_in), .dout(uncacheable_miss_ff));
rvdff_fpga #(3) mb_rep_wayf2_ff (.*, .clk(fetch_f1_f2_c1_clk), .clken(fetch_f1_f2_c1_clken), .rawclk(clk), .din ({way_status_mb_in[2:0]}), .dout({way_status_mb_ff[2:0]}));
rvdff_fpga #(4) mb_tagv_ff (.*, .clk(fetch_f1_f2_c1_clk), .clken(fetch_f1_f2_c1_clken), .rawclk(clk), .din ({tagv_mb_in[3:0]}), .dout({tagv_mb_ff[3:0]}));
rvdff_fpga #(1) ifu_iccm_acc_ff (.*, .clk(fetch_f1_f2_c1_clk), .clken(fetch_f1_f2_c1_clken), .rawclk(clk), .din(ifc_iccm_access_f1), .dout(ifc_iccm_access_f2));
rvdff_fpga #(1) ifu_iccm_reg_acc_ff (.*, .clk(fetch_f1_f2_c1_clk), .clken(fetch_f1_f2_c1_clken), .rawclk(clk), .din(ifc_region_acc_fault_final_f1), .dout(ifc_region_acc_fault_f2));
rvdffe #(31) imb_f2_ff (.*, .en(fetch_f1_f2_c1_clken), .din ({imb_in[31:1]}), .dout({imb_ff[31:1]}));
assign ifc_fetch_req_qual_f1 = ifc_fetch_req_f1 & ~((miss_state == CRIT_WRD_RDY) & flush_final_f2) ;// & ~exu_flush_final ; assign ifc_fetch_req_qual_f1 = ifc_fetch_req_f1 & ~((miss_state == CRIT_WRD_RDY) & flush_final_f2) ;// & ~exu_flush_final ;
rvdff #(1) fetch_req_f2_ff (.*, .clk(active_clk), .din(ifc_fetch_req_qual_f1), .dout(ifc_fetch_req_f2_raw)); rvdff #(1) fetch_req_f2_ff (.*, .clk(active_clk), .din(ifc_fetch_req_qual_f1), .dout(ifc_fetch_req_f2_raw));
assign ifc_fetch_req_f2 = ifc_fetch_req_f2_raw & ~exu_flush_final ; assign ifc_fetch_req_f2 = ifc_fetch_req_f2_raw & ~exu_flush_final ;
rvdff #(1) ifu_iccm_acc_ff (.*, .clk(fetch_f1_f2_c1_clk), .din(ifc_iccm_access_f1), .dout(ifc_iccm_access_f2));
rvdff #(1) ifu_iccm_reg_acc_ff (.*, .clk(fetch_f1_f2_c1_clk), .din(ifc_region_acc_fault_final_f1), .dout(ifc_region_acc_fault_f2));
assign ifu_ic_req_addr_f2[31:3] = {imb_ff[31:6] , ic_req_addr_bits_5_3[5:3] }; assign ifu_ic_req_addr_f2[31:3] = {imb_ff[31:6] , ic_req_addr_bits_5_3[5:3] };
assign ifu_ic_mb_empty = ((miss_state == HIT_U_MISS) & ~(ifu_wr_en_new & last_beat)) | ~miss_pending ; assign ifu_ic_mb_empty = ((miss_state == HIT_U_MISS) & ~(ifu_wr_en_new & last_beat)) | ~miss_pending ;
@ -584,7 +583,7 @@ module ifu_mem_ctl
rvdff #(1) sel_mb_addr_flop (.*, .clk(free_clk), .din({sel_mb_addr}), .dout({sel_mb_addr_ff})); rvdff #(1) sel_mb_addr_flop (.*, .clk(free_clk), .din({sel_mb_addr}), .dout({sel_mb_addr_ff}));
assign ic_rw_addr[31:3] = ifu_ic_rw_int_addr[31:3] ; assign ic_rw_addr[31:2] = ifu_ic_rw_int_addr[31:2] ;
genvar i ; genvar i ;
@ -730,9 +729,6 @@ assign ic_fetch_val_f2[0] = fetch_req_f2_qual ;
assign byp_data_first_c1_clken = write_byp_first_data; assign byp_data_first_c1_clken = write_byp_first_data;
assign byp_data_second_c1_clken = write_byp_second_data; assign byp_data_second_c1_clken = write_byp_second_data;
rvclkhdr byp_data_first_c1_cgc ( .en(byp_data_first_c1_clken), .l1clk(byp_data_first_c1_clk), .* );
rvclkhdr byp_data_second_c1_cgc ( .en(byp_data_second_c1_clken), .l1clk(byp_data_second_c1_clk), .* );
assign byp_tag_ff[IFU_BUS_TAG-1:0] = IFU_BUS_TAG'({imb_ff[5:4] , 1'b0}); assign byp_tag_ff[IFU_BUS_TAG-1:0] = IFU_BUS_TAG'({imb_ff[5:4] , 1'b0});
assign write_byp_first_data = axi_ifu_wr_en_new & ({byp_tag_ff[IFU_BUS_TAG-1:1],1'b0} == ifu_axi_rid_ff[IFU_BUS_TAG-1:0]); assign write_byp_first_data = axi_ifu_wr_en_new & ({byp_tag_ff[IFU_BUS_TAG-1:1],1'b0} == ifu_axi_rid_ff[IFU_BUS_TAG-1:0]);
assign write_byp_second_data = axi_ifu_wr_en_new & ({byp_tag_ff[IFU_BUS_TAG-1:1],1'b1} == ifu_axi_rid_ff[IFU_BUS_TAG-1:0]); assign write_byp_second_data = axi_ifu_wr_en_new & ({byp_tag_ff[IFU_BUS_TAG-1:1],1'b1} == ifu_axi_rid_ff[IFU_BUS_TAG-1:0]);
@ -1006,8 +1002,6 @@ assign iccm_single_ecc_error = '0;
assign axi_ifu_bus_clk_en = ifu_bus_clk_en ; assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
rvclkhdr axi_clk(.en(axi_ifu_bus_clk_en),
.l1clk(axiclk), .*);
rvdff #(1) axi_clken_ff (.*, .clk(free_clk), .din(axi_ifu_bus_clk_en), .dout(axi_ifu_bus_clk_en_ff)); rvdff #(1) axi_clken_ff (.*, .clk(free_clk), .din(axi_ifu_bus_clk_en), .dout(axi_ifu_bus_clk_en_ff));
@ -1017,12 +1011,18 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
assign ifc_axi_ic_req_ff_in = (ic_act_miss_f2 | axi_cmd_req_hold | ifc_axi_ic_req_ff2) & ~((axi_cmd_beat_count==3'b111) & ifu_axi_arvalid & ifu_axi_arready & miss_pending); assign ifc_axi_ic_req_ff_in = (ic_act_miss_f2 | axi_cmd_req_hold | ifc_axi_ic_req_ff2) & ~((axi_cmd_beat_count==3'b111) & ifu_axi_arvalid & ifu_axi_arready & miss_pending);
rvdff #(1) axi_ic_req_ff2(.*, .clk(axiclk), .din(ifc_axi_ic_req_ff_in), .dout(ifc_axi_ic_req_ff2));
assign axi_cmd_req_in = (ic_act_miss_f2 | axi_cmd_req_hold) & ~axi_cmd_sent ; // hold until first command sent assign axi_cmd_req_in = (ic_act_miss_f2 | axi_cmd_req_hold) & ~axi_cmd_sent ; // hold until first command sent
// changes for making the axi blocking // changes for making the axi blocking
rvdff #(1) axi_cmd_req_ff (.*, .clk(free_clk), .din(axi_cmd_req_in), .dout(axi_cmd_req_hold)); rvdff #(1) axi_cmd_req_ff (.*, .clk(free_clk), .din(axi_cmd_req_in), .dout(axi_cmd_req_hold));
`ifndef RV_FPGA_OPTIMIZE
rvclkhdr fetch_f1_f2_c1_cgc ( .en(fetch_f1_f2_c1_clken), .l1clk(fetch_f1_f2_c1_clk), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr axi_clk(.en(axi_ifu_bus_clk_en),.l1clk(axiclk), .*); // ifndef FPGA_OPTIMIZE
rvclkhdr axi_clk_reset(.en(axi_ifu_bus_clk_en | ic_act_miss_f2), .l1clk(axiclk_reset), .*); // ifndef FPGA_OPTIMIZE
`endif
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// logic axi_cmd_rsp_pend; // logic axi_cmd_rsp_pend;
// `ifdef RV_BUILD_SVC // `ifdef RV_BUILD_SVC
@ -1048,12 +1048,13 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
assign ifu_axi_arlock = '0; assign ifu_axi_arlock = '0;
// IFU Write channels - not needed, so 00 out // IFU Write channels - not needed, so 00 out
rvdff #(1) axi_rdy_ff (.*, .clk(axiclk), .din(ifu_axi_arready), .dout(ifu_axi_arready_unq_ff)); rvdff_fpga #(1) axi_ic_req_ff2 (.*, .clk(axiclk), .clken(axi_ifu_bus_clk_en), .rawclk(clk), .din(ifc_axi_ic_req_ff_in), .dout(ifc_axi_ic_req_ff2));
rvdff #(1) axi_rsp_vld_ff (.*, .clk(axiclk), .din(ifu_axi_rvalid), .dout(ifu_axi_rvalid_unq_ff)); rvdff_fpga #(1) axi_rdy_ff (.*, .clk(axiclk), .clken(axi_ifu_bus_clk_en), .rawclk(clk), .din(ifu_axi_arready), .dout(ifu_axi_arready_unq_ff));
rvdff #(1) axi_cmd_ff (.*, .clk(axiclk), .din(ifu_axi_arvalid), .dout(ifu_axi_arvalid_ff)); rvdff_fpga #(1) axi_rsp_vld_ff (.*, .clk(axiclk), .clken(axi_ifu_bus_clk_en), .rawclk(clk), .din(ifu_axi_rvalid), .dout(ifu_axi_rvalid_unq_ff));
rvdff #(2) scvi_rsp_cmd_ff (.*, .clk(axiclk), .din(ifu_axi_rresp[1:0]), .dout(ifu_axi_rresp_ff[1:0])); rvdff_fpga #(1) axi_cmd_ff (.*, .clk(axiclk), .clken(axi_ifu_bus_clk_en), .rawclk(clk), .din(ifu_axi_arvalid), .dout(ifu_axi_arvalid_ff));
rvdff #(IFU_BUS_TAG) scvi_rsp_tag_ff (.*, .clk(axiclk), .din(ifu_axi_rid[IFU_BUS_TAG-1:0]), .dout(ifu_axi_rid_ff[IFU_BUS_TAG-1:0])); rvdff_fpga #(2) scvi_rsp_cmd_ff (.*, .clk(axiclk), .clken(axi_ifu_bus_clk_en), .rawclk(clk), .din(ifu_axi_rresp[1:0]), .dout(ifu_axi_rresp_ff[1:0]));
rvdff #(64) axi_data_ff (.*, .clk(axiclk), .din(ifu_axi_rdata[63:0]), .dout(ifu_axi_rdata_ff[63:0])); rvdff_fpga #(IFU_BUS_TAG) scvi_rsp_tag_ff (.*, .clk(axiclk), .clken(axi_ifu_bus_clk_en), .rawclk(clk), .din(ifu_axi_rid[IFU_BUS_TAG-1:0]), .dout(ifu_axi_rid_ff[IFU_BUS_TAG-1:0]));
rvdff_fpga #(64) axi_data_ff (.*, .clk(axiclk), .clken(axi_ifu_bus_clk_en), .rawclk(clk), .din(ifu_axi_rdata[63:0]), .dout(ifu_axi_rdata_ff[63:0]));
@ -1077,7 +1078,9 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
assign axi_new_rd_addr_count[2:0] = ~miss_pending ? {imb_ff[5:4],1'b0} : axi_inc_rd_addr_cnt ? (axi_rd_addr_count[2:0] + 3'b001) : axi_rd_addr_count[2:0]; assign axi_new_rd_addr_count[2:0] = ~miss_pending ? {imb_ff[5:4],1'b0} : axi_inc_rd_addr_cnt ? (axi_rd_addr_count[2:0] + 3'b001) : axi_rd_addr_count[2:0];
rvdffs #(3) axi_rd_addr_ff (.*, .en(1'b1), .clk(axiclk_reset), .din ({axi_new_rd_addr_count[2:0]}), .dout({axi_rd_addr_count[2:0]}));
rvdff_fpga #(3) axi_cmd_beat_ff (.*, .clk(axiclk_reset), .clken(axi_ifu_bus_clk_en | ic_act_miss_f2), .rawclk(clk), .din ({axi_new_cmd_beat_count[2:0]}), .dout({axi_cmd_beat_count[2:0]}));
rvdffs_fpga #(3) axi_rd_addr_ff (.*, .en(1'b1), .clk(axiclk_reset), .clken(axi_ifu_bus_clk_en | ic_act_miss_f2), .rawclk(clk), .din ({axi_new_rd_addr_count[2:0]}), .dout({axi_rd_addr_count[2:0]}));
// command beat Count // command beat Count
assign axi_inc_cmd_beat_cnt = ifu_axi_arvalid & ifu_axi_arready & miss_pending; assign axi_inc_cmd_beat_cnt = ifu_axi_arvalid & ifu_axi_arready & miss_pending;
@ -1090,12 +1093,6 @@ assign axi_ifu_bus_clk_en = ifu_bus_clk_en ;
({3{axi_inc_cmd_beat_cnt}} & (axi_cmd_beat_count[2:0] + 3'b001)) | ({3{axi_inc_cmd_beat_cnt}} & (axi_cmd_beat_count[2:0] + 3'b001)) |
({3{axi_hold_cmd_beat_cnt}} & axi_cmd_beat_count[2:0]) ; ({3{axi_hold_cmd_beat_cnt}} & axi_cmd_beat_count[2:0]) ;
rvclkhdr axi_clk_reset(.en(axi_ifu_bus_clk_en | ic_act_miss_f2),
.l1clk(axiclk_reset), .*);
rvdff #(3) axi_cmd_beat_ff (.*, .clk(axiclk_reset), .din ({axi_new_cmd_beat_count[2:0]}),
.dout({axi_cmd_beat_count[2:0]}));
assign req_addr_count[2:0] = axi_rd_addr_count[2:0] ; assign req_addr_count[2:0] = axi_rd_addr_count[2:0] ;
@ -1235,14 +1232,22 @@ assign ic_write_stall = ifu_wr_en_new & ~(((miss_state== CRIT_BYP_OK) & ~(ifu_
genvar j; genvar j;
for (i=0 ; i<ICACHE_TAG_DEPTH/8 ; i++) begin : CLK_GRP_WAY_STATUS for (i=0 ; i<ICACHE_TAG_DEPTH/8 ; i++) begin : CLK_GRP_WAY_STATUS
assign way_status_clken[i] = (ifu_status_wr_addr_ff[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW+3] == i ); assign way_status_clken[i] = (ifu_status_wr_addr_ff[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW+3] == i );
rvclkhdr way_status_cgc ( .en(way_status_clken[i]), .l1clk(way_status_clk[i]), .* );
`ifndef RV_FPGA_OPTIMIZE
rvclkhdr way_status_cgc ( .en(way_status_clken[i]), .l1clk(way_status_clk[i]), .* ); // ifndef FPGA_OPTIMIZE
`endif
for (j=0 ; j<8 ; j++) begin : WAY_STATUS for (j=0 ; j<8 ; j++) begin : WAY_STATUS
rvdffs #(3) ic_way_status (.*,
rvdffs_fpga #(3) ic_way_status (.*,
.clk(way_status_clk[i]), .clk(way_status_clk[i]),
.clken(way_status_clken[i]),
.rawclk(clk),
.en(((ifu_status_wr_addr_ff[ICACHE_TAG_LOW+2:ICACHE_TAG_LOW] == j) & way_status_wr_en_ff)), .en(((ifu_status_wr_addr_ff[ICACHE_TAG_LOW+2:ICACHE_TAG_LOW] == j) & way_status_wr_en_ff)),
.din(way_status_new_ff[2:0]), .din(way_status_new_ff[2:0]),
.dout(way_status_out[8*i+j])); .dout(way_status_out[8*i+j]));
end // WAY_STATUS end // WAY_STATUS
end // CLK_GRP_WAY_STATUS end // CLK_GRP_WAY_STATUS
@ -1297,34 +1302,44 @@ assign ifu_ic_rw_int_addr_w_debug[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW] = ((ic_debug
assign tag_valid_w3_clken[i] = (((ifu_ic_rw_int_addr_ff[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW+5] == i ) & ifu_tag_wren_ff[3] ) | assign tag_valid_w3_clken[i] = (((ifu_ic_rw_int_addr_ff[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW+5] == i ) & ifu_tag_wren_ff[3] ) |
((perr_ic_index_ff [ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW+5] == i ) & perr_err_inv_way[3]) | reset_all_tags); ((perr_ic_index_ff [ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW+5] == i ) & perr_err_inv_way[3]) | reset_all_tags);
rvclkhdr way0_status_cgc ( .en(tag_valid_w0_clken[i]), .l1clk(tag_valid_w0_clk[i]), .* ); `ifndef RV_FPGA_OPTIMIZE
rvclkhdr way1_status_cgc ( .en(tag_valid_w1_clken[i]), .l1clk(tag_valid_w1_clk[i]), .* ); rvclkhdr way0_status_cgc ( .en(tag_valid_w0_clken[i]), .l1clk(tag_valid_w0_clk[i]), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr way2_status_cgc ( .en(tag_valid_w2_clken[i]), .l1clk(tag_valid_w2_clk[i]), .* ); rvclkhdr way1_status_cgc ( .en(tag_valid_w1_clken[i]), .l1clk(tag_valid_w1_clk[i]), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr way3_status_cgc ( .en(tag_valid_w3_clken[i]), .l1clk(tag_valid_w3_clk[i]), .* ); rvclkhdr way2_status_cgc ( .en(tag_valid_w2_clken[i]), .l1clk(tag_valid_w2_clk[i]), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr way3_status_cgc ( .en(tag_valid_w3_clken[i]), .l1clk(tag_valid_w3_clk[i]), .* ); // ifndef FPGA_OPTIMIZE
`endif
for (j=0 ; j<32 ; j++) begin : TAG_VALID for (j=0 ; j<32 ; j++) begin : TAG_VALID
rvdffs #(1) ic_way0_tagvalid_dup (.*, rvdffs_fpga #(1) ic_way0_tagvalid_dup (.*,
.clk(tag_valid_w0_clk[i]), .clk(tag_valid_w0_clk[i]),
.clken(tag_valid_w0_clken[i]),
.rawclk(clk),
.en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[0] ) | .en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[0] ) |
((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[0]) | reset_all_tags), ((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[0]) | reset_all_tags),
.din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate), .din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate),
.dout(ic_tag_valid_out[0][32*i+j])); .dout(ic_tag_valid_out[0][32*i+j]));
rvdffs #(1) ic_way1_tagvalid_dup (.*, rvdffs_fpga #(1) ic_way1_tagvalid_dup (.*,
.clk(tag_valid_w1_clk[i]), .clk(tag_valid_w1_clk[i]),
.clken(tag_valid_w1_clken[i]),
.rawclk(clk),
.en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[1] ) | .en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[1] ) |
((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[1]) | reset_all_tags), ((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[1]) | reset_all_tags),
.din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate), .din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate),
.dout(ic_tag_valid_out[1][32*i+j])); .dout(ic_tag_valid_out[1][32*i+j]));
rvdffs #(1) ic_way2_tagvalid_dup (.*, rvdffs_fpga #(1) ic_way2_tagvalid_dup (.*,
.clk(tag_valid_w2_clk[i]), .clk(tag_valid_w2_clk[i]),
.clken(tag_valid_w2_clken[i]),
.rawclk(clk),
.en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[2] ) | .en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[2] ) |
((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[2]) | reset_all_tags), ((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[2]) | reset_all_tags),
.din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate), .din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate),
.dout(ic_tag_valid_out[2][32*i+j])); .dout(ic_tag_valid_out[2][32*i+j]));
rvdffs #(1) ic_way3_tagvalid_dup (.*, rvdffs_fpga #(1) ic_way3_tagvalid_dup (.*,
.clk(tag_valid_w3_clk[i]), .clk(tag_valid_w3_clk[i]),
.clken(tag_valid_w3_clken[i]),
.rawclk(clk),
.en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[3] ) | .en(((ifu_ic_rw_int_addr_ff[ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & ifu_tag_wren_ff[3] ) |
((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[3]) | reset_all_tags), ((perr_ic_index_ff [ICACHE_TAG_LOW+4:ICACHE_TAG_LOW] == j) & perr_err_inv_way[3]) | reset_all_tags),
.din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate), .din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate),
@ -1417,7 +1432,8 @@ assign ic_debug_ic_array_sel_word2_in = (ic_debug_addr[3:2] == 2'b10) & ic_debug
assign ic_debug_ic_array_sel_word3_in = (ic_debug_addr[3:2] == 2'b11) & ic_debug_rd_en & ~ic_debug_tag_array ; assign ic_debug_ic_array_sel_word3_in = (ic_debug_addr[3:2] == 2'b11) & ic_debug_rd_en & ~ic_debug_tag_array ;
assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array ; assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array ;
rvdffe #(09) ifu_debug_sel_ff (.*, .en (debug_c1_clken), rvdffe #(09) ifu_debug_sel_ff (.*,
.en (debug_c1_clken),
.din ({ic_debug_ic_array_sel_word0_in, .din ({ic_debug_ic_array_sel_word0_in,
ic_debug_ic_array_sel_word1_in, ic_debug_ic_array_sel_word1_in,
ic_debug_ic_array_sel_word2_in, ic_debug_ic_array_sel_word2_in,
@ -1451,7 +1467,8 @@ assign ifu_ic_debug_rd_data_in[41:0] = ( {42{ic_debug_ict_array_sel_ff }} & {
( {42{ic_debug_ic_array_sel_word2 }} & {ic_rd_data [125:84]}) | ( {42{ic_debug_ic_array_sel_word2 }} & {ic_rd_data [125:84]}) |
( {42{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [167:126]}) ; ( {42{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [167:126]}) ;
rvdffe #(42) ifu_debug_data_ff (.*, .en (debug_data_clken), rvdffe #(42) ifu_debug_data_ff (.*,
.en (debug_data_clken),
.din ({ .din ({
ifu_ic_debug_rd_data_in[41:0] ifu_ic_debug_rd_data_in[41:0]
}), }),
@ -1467,7 +1484,8 @@ assign ifu_ic_debug_rd_data_in[33:0] = ( {34{ic_debug_ict_array_sel_ff }} & {
( {34{ic_debug_ic_array_sel_word2 }} & {ic_rd_data [101:68]}) | ( {34{ic_debug_ic_array_sel_word2 }} & {ic_rd_data [101:68]}) |
( {34{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [135:102]}) ; ( {34{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [135:102]}) ;
rvdffe #(34) ifu_debug_data_ff (.*, .en (debug_data_clken), rvdffe #(34) ifu_debug_data_ff (.*,
.en (debug_data_clken),
.din ({ .din ({
ifu_ic_debug_rd_data_in[33:0] ifu_ic_debug_rd_data_in[33:0]
}), }),
@ -1476,8 +1494,8 @@ rvdffe #(34) ifu_debug_data_ff (.*, .en (debug_data_clken),
})); }));
`endif `endif
assign debug_data_clken = ic_debug_rd_en_ff; assign debug_data_clken = ic_debug_rd_en_ff;
rvclkhdr debug_data_c1_cgc ( .en(debug_data_clken), .l1clk(debug_data_clk), .* );
rvdff #(1) ifu_debug_valid_ff (.*, .clk(free_clk), rvdff #(1) ifu_debug_valid_ff (.*, .clk(free_clk),
.din ({ .din ({

54
design/lib/ahb_to_axi4.sv
View File

@ -157,7 +157,6 @@ module ahb_to_axi4 #(parameter TAG = 1) (
endcase endcase
end // always_comb begin end // always_comb begin
rvdffs #($bits(state_t)) state_reg (.*, .din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clk(ahb_clk));
assign master_wstrb[7:0] = ({8{ahb_hsize_q[2:0] == 3'b0}} & (8'b1 << ahb_haddr_q[2:0])) | assign master_wstrb[7:0] = ({8{ahb_hsize_q[2:0] == 3'b0}} & (8'b1 << ahb_haddr_q[2:0])) |
({8{ahb_hsize_q[2:0] == 3'b1}} & (8'b11 << ahb_haddr_q[2:0])) | ({8{ahb_hsize_q[2:0] == 3'b1}} & (8'b11 << ahb_haddr_q[2:0])) |
@ -181,24 +180,35 @@ module ahb_to_axi4 #(parameter TAG = 1) (
(ahb_hresp_q & ~ahb_hready_q); // This is for second cycle of hresp protocol (ahb_hresp_q & ~ahb_hready_q); // This is for second cycle of hresp protocol
// Buffer signals - needed for the read data and ECC error response // Buffer signals - needed for the read data and ECC error response
rvdff #(.WIDTH(64)) buf_rdata_ff (.din(axi_rdata[63:0]), .dout(buf_rdata[63:0]), .clk(buf_rdata_clk), .*);
rvdff #(.WIDTH(1)) buf_read_error_ff(.din(buf_read_error_in), .dout(buf_read_error), .clk(ahb_clk), .*); // buf_read_error will be high only one cycle
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer. // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
rvdff #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(ahb_clk), .*); rvdff_fpga #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(ahb_clk), .*); rvdff_fpga #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff #(.WIDTH(2)) htrans_ff (.din(ahb_htrans_in[1:0]), .dout(ahb_htrans_q[1:0]), .clk(ahb_clk), .*); rvdff_fpga #(.WIDTH(2)) htrans_ff (.din(ahb_htrans_in[1:0]), .dout(ahb_htrans_q[1:0]), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff #(.WIDTH(3)) hsize_ff (.din(ahb_hsize[2:0]), .dout(ahb_hsize_q[2:0]), .clk(ahb_addr_clk), .*); rvdff_fpga #(.WIDTH(3)) hsize_ff (.din(ahb_hsize[2:0]), .dout(ahb_hsize_q[2:0]), .clk(ahb_addr_clk), .clken(ahb_bus_addr_clk_en), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(ahb_addr_clk), .*); rvdff_fpga #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(ahb_addr_clk), .clken(ahb_bus_addr_clk_en), .rawclk(clk), .*);
rvdff #(.WIDTH(32)) haddr_ff (.din(ahb_haddr[31:0]), .dout(ahb_haddr_q[31:0]), .clk(ahb_addr_clk), .*); rvdff_fpga #(.WIDTH(32)) haddr_ff (.din(ahb_haddr[31:0]), .dout(ahb_haddr_q[31:0]), .clk(ahb_addr_clk), .clken(ahb_bus_addr_clk_en), .rawclk(clk), .*);
rvdffs_fpga #($bits(state_t)) state_reg (.din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(64)) buf_rdata_ff (.din(axi_rdata[63:0]), .dout(buf_rdata[63:0]), .clk(buf_rdata_clk), .clken(buf_rdata_clk_en), .rawclk(clk), .*);
// buf_read_error will be high only one cycle
rvdff_fpga #(.WIDTH(1)) buf_read_error_ff(.din(buf_read_error_in), .dout(buf_read_error),.clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
// Clock header logic // Clock header logic
assign ahb_bus_addr_clk_en = bus_clk_en & (ahb_hready & ahb_htrans[1]); assign ahb_bus_addr_clk_en = bus_clk_en & (ahb_hready & ahb_htrans[1]);
assign buf_rdata_clk_en = bus_clk_en & buf_rdata_en; assign buf_rdata_clk_en = bus_clk_en & buf_rdata_en;
rvclkhdr ahb_cgc (.en(bus_clk_en), .l1clk(ahb_clk), .*); `ifdef RV_FPGA_OPTIMIZE
rvclkhdr ahb_addr_cgc (.en(ahb_bus_addr_clk_en), .l1clk(ahb_addr_clk), .*); assign ahb_clk = 1'b0;
rvclkhdr buf_rdata_cgc (.en(buf_rdata_clk_en), .l1clk(buf_rdata_clk), .*); assign ahb_addr_clk = 1'b0;
assign buf_rdata_clk = 1'b0;
assign bus_clk = 1'b0;
`else
rvclkhdr ahb_cgc (.en(bus_clk_en), .l1clk(ahb_clk), .*); // ifndef FPGA_OPTIMIZE
rvclkhdr ahb_addr_cgc (.en(ahb_bus_addr_clk_en), .l1clk(ahb_addr_clk), .*); // ifndef FPGA_OPTIMIZE
rvclkhdr buf_rdata_cgc (.en(buf_rdata_clk_en), .l1clk(buf_rdata_clk), .*); // ifndef FPGA_OPTIMIZE
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*); // ifndef FPGA_OPTIMIZE
`endif
// Address check dccm // Address check dccm
rvrangecheck #(.CCM_SADR(`RV_DCCM_SADR), rvrangecheck #(.CCM_SADR(`RV_DCCM_SADR),
@ -233,12 +243,19 @@ module ahb_to_axi4 #(parameter TAG = 1) (
assign cmdbuf_rst = (((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en) | (ahb_hresp & ~cmdbuf_write); assign cmdbuf_rst = (((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en) | (ahb_hresp & ~cmdbuf_write);
assign cmdbuf_full = (cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready))); assign cmdbuf_full = (cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)));
rvdffsc #(.WIDTH(1)) cmdbuf_vldff (.din(1'b1), .dout(cmdbuf_vld), .en(cmdbuf_wr_en), .clear(cmdbuf_rst), .clk(bus_clk), .*); rvdffsc_fpga #(.WIDTH(1)) cmdbuf_vldff (.din(1'b1), .clear(cmdbuf_rst), .dout(cmdbuf_vld), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs #(.WIDTH(1)) cmdbuf_writeff (.din(ahb_hwrite_q), .dout(cmdbuf_write), .en(cmdbuf_wr_en), .clk(bus_clk), .*); rvdffs_fpga #(.WIDTH(1)) cmdbuf_writeff (.din(ahb_hwrite_q), .dout(cmdbuf_write), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs #(.WIDTH(2)) cmdbuf_sizeff (.din(ahb_hsize_q[1:0]), .dout(cmdbuf_size[1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*); rvdffs_fpga #(.WIDTH(2)) cmdbuf_sizeff (.din(ahb_hsize_q[1:0]), .dout(cmdbuf_size[1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs #(.WIDTH(8)) cmdbuf_wstrbff (.din(master_wstrb[7:0]), .dout(cmdbuf_wstrb[7:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*); rvdffs_fpga #(.WIDTH(8)) cmdbuf_wstrbff (.din(master_wstrb[7:0]), .dout(cmdbuf_wstrb[7:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) cmdbuf_addrff (.din(ahb_haddr_q[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
rvdffe #(.WIDTH(64)) cmdbuf_wdataff (.din(ahb_hwdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*); // REVIEW : was 2 clock headers
// rvdffe #(.WIDTH(32)) cmdbuf_addrff (.din(ahb_haddr_q[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
// rvdffe #(.WIDTH(64)) cmdbuf_wdataff (.din(ahb_hwdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
rvdffe #(.WIDTH(32)) cmdbuf_addrff (.din(ahb_haddr_q[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
rvdffe #(.WIDTH(64)) cmdbuf_wdataff (.din(ahb_hwdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
// AXI Write Command Channel // AXI Write Command Channel
assign axi_awvalid = cmdbuf_vld & cmdbuf_write; assign axi_awvalid = cmdbuf_vld & cmdbuf_write;
@ -267,7 +284,6 @@ module ahb_to_axi4 #(parameter TAG = 1) (
assign axi_rready = 1'b1; assign axi_rready = 1'b1;
// Clock header logic // Clock header logic
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
`ifdef ASSERT_ON `ifdef ASSERT_ON
property ahb_error_protocol; property ahb_error_protocol;

77
design/lib/axi4_to_ahb.sv
View File

@ -249,8 +249,21 @@ module axi4_to_ahb #(parameter TAG = 1) (
// Clock header logic // Clock header logic
assign bus_write_clk_en = bus_clk_en & ((axi_awvalid & axi_awready) | (axi_wvalid & axi_wready)); assign bus_write_clk_en = bus_clk_en & ((axi_awvalid & axi_awready) | (axi_wvalid & axi_wready));
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*); `ifdef RV_FPGA_OPTIMIZE
rvclkhdr bus_write_cgc (.en(bus_write_clk_en), .l1clk(bus_write_clk), .*); assign bus_clk = 1'b0;
assign bus_write_clk = 1'b0;
assign buf_clk = 1'b0;
assign ahbm_clk = 1'b0;
assign ahbm_addr_clk = 1'b0;
assign ahbm_data_clk = 1'b0;
`else
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*); // ifndef FGPA_OPTIMIZE
rvclkhdr bus_write_cgc (.en(bus_write_clk_en), .l1clk(bus_write_clk), .*); // ifndef FGPA_OPTIMIZE
rvclkhdr buf_cgc (.en(buf_clken), .l1clk(buf_clk), .*); // ifndef FGPA_OPTIMIZE
rvclkhdr ahbm_cgc (.en(bus_clk_en), .l1clk(ahbm_clk), .*); // ifndef FGPA_OPTIMIZE
rvclkhdr ahbm_addr_cgc (.en(ahbm_addr_clken), .l1clk(ahbm_addr_clk), .*); // ifndef FGPA_OPTIMIZE
rvclkhdr ahbm_data_cgc (.en(ahbm_data_clken), .l1clk(ahbm_data_clk), .*); // ifndef FGPA_OPTIMIZE
`endif
// FIFO state machine // FIFO state machine
@ -405,39 +418,39 @@ module axi4_to_ahb #(parameter TAG = 1) (
assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ; assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ;
rvdffsc_fpga #(1) wrbuf_vldff (.din(1'b1), .clear(wrbuf_rst), .dout(wrbuf_vld), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(1) wrbuf_data_vldff (.din(1'b1), .clear(wrbuf_rst), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(TAG) wrbuf_tagff (.din(axi_awid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(3) wrbuf_sizeff (.din(axi_awsize[2:0]), .dout(wrbuf_size[2:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(8) wrbuf_byteenff (.din(axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #($bits(state_t)) buf_state_ff (.din(buf_nxtstate), .clear(buf_rst), .dout({buf_state}), .en(buf_state_en), .clk(ahbm_clk),.clken(bus_clk_en), .rawclk(clk), .*);
rvdffsc #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(bus_clk), .*); rvdffs_fpga #(1) buf_writeff (.din(buf_write_in), .dout(buf_write), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffsc #(.WIDTH(1)) wrbuf_data_vldff(.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_rst), .clk(bus_clk), .*); rvdffs_fpga #(TAG) buf_tagff (.din(buf_tag_in[TAG-1:0]), .dout(buf_tag[TAG-1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs #(.WIDTH(TAG)) wrbuf_tagff (.din(axi_awid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en), .clk(bus_clk), .*); rvdffs_fpga #(2) buf_sizeff (.din(buf_size_in[1:0]), .dout(buf_size[1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs #(.WIDTH(3)) wrbuf_sizeff (.din(axi_awsize[2:0]), .dout(wrbuf_size[2:0]), .en(wrbuf_en), .clk(bus_clk), .*); rvdffs_fpga #(1) buf_alignedff (.din(buf_aligned_in), .dout(buf_aligned), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) wrbuf_addrff (.din(axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en), .clk(bus_clk), .*); rvdffs_fpga #(8) buf_byteenff (.din(buf_byteen_in[7:0]), .dout(buf_byteen[7:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffe #(.WIDTH(64)) wrbuf_dataff (.din(axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en), .clk(bus_clk), .*); rvdffs_fpga #(1) slvbuf_writeff (.din(buf_write), .dout(slvbuf_write), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs #(.WIDTH(8)) wrbuf_byteenff (.din(axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(bus_clk), .*); rvdffs_fpga #(TAG) slvbuf_tagff (.din(buf_tag[TAG-1:0]), .dout(slvbuf_tag[TAG-1:0]), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
rvdffs #(.WIDTH(32)) last_bus_addrff (.din(ahb_haddr[31:0]), .dout(last_bus_addr[31:0]), .en(last_addr_en), .clk(ahbm_clk), .*); rvdffs_fpga #(1) slvbuf_errorff (.din(slvbuf_error_in), .dout(slvbuf_error), .en(slvbuf_error_en), .clk(ahbm_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffsc_fpga #(1) buf_cmd_doneff (.din(1'b1), .clear(cmd_done_rst), .dout(cmd_doneQ),.en(cmd_done), .clk(ahbm_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffs_fpga #(3) buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en), .clk(ahbm_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(ahbm_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(2) htrans_ff (.din(ahb_htrans[1:0]), .dout(ahb_htrans_q[1:0]), .clk(ahbm_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(ahbm_addr_clk), .clken(ahbm_addr_clken), .rawclk(clk), .*);
rvdff_fpga #(1) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(ahbm_clk), .clken(bus_clk_en), .rawclk(clk), .*);
rvdffe #(.WIDTH(32)) last_bus_addrff (.din(ahb_haddr[31:0]), .dout(last_bus_addr[31:0]), .en(last_addr_en & bus_clk_en), .*);
rvdffsc #(.WIDTH($bits(state_t))) buf_state_ff (.din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clear(buf_rst), .clk(ahbm_clk), .*);
rvdffs #(.WIDTH(1)) buf_writeff (.din(buf_write_in), .dout(buf_write), .en(buf_wr_en), .clk(buf_clk), .*);
rvdffs #(.WIDTH(TAG)) buf_tagff (.din(buf_tag_in[TAG-1:0]), .dout(buf_tag[TAG-1:0]), .en(buf_wr_en), .clk(buf_clk), .*);
rvdffe #(.WIDTH(32)) buf_addrff (.din(buf_addr_in[31:0]), .dout(buf_addr[31:0]), .en(buf_wr_en & bus_clk_en), .*);
rvdffs #(.WIDTH(2)) buf_sizeff (.din(buf_size_in[1:0]), .dout(buf_size[1:0]), .en(buf_wr_en), .clk(buf_clk), .*);
rvdffs #(.WIDTH(1)) buf_alignedff (.din(buf_aligned_in), .dout(buf_aligned), .en(buf_wr_en), .clk(buf_clk), .*);
rvdffs #(.WIDTH(8)) buf_byteenff (.din(buf_byteen_in[7:0]), .dout(buf_byteen[7:0]), .en(buf_wr_en), .clk(buf_clk), .*);
rvdffe #(.WIDTH(64)) buf_dataff (.din(buf_data_in[63:0]), .dout(buf_data[63:0]), .en(buf_data_wr_en & bus_clk_en), .*); rvdffe #(.WIDTH(64)) buf_dataff (.din(buf_data_in[63:0]), .dout(buf_data[63:0]), .en(buf_data_wr_en & bus_clk_en), .*);
rvdffe #(.WIDTH(32)) wrbuf_addrff (.din(axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & bus_clk_en), .*);
rvdffe #(.WIDTH(64)) wrbuf_dataff (.din(axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & bus_clk_en), .*);
rvdffe #(.WIDTH(64)) hrdata_ff (.din(ahb_hrdata[63:0]), .dout(ahb_hrdata_q[63:0]), .en(ahbm_data_clken), .*);
rvdffs #(.WIDTH(1)) slvbuf_writeff (.din(buf_write), .dout(slvbuf_write), .en(slvbuf_wr_en), .clk(buf_clk), .*); rvdffe #(.WIDTH(32)) buf_addrff (.din(buf_addr_in[31:0]), .dout(buf_addr[31:0]), .en(buf_wr_en & bus_clk_en), .*);
rvdffs #(.WIDTH(TAG)) slvbuf_tagff (.din(buf_tag[TAG-1:0]), .dout(slvbuf_tag[TAG-1:0]), .en(slvbuf_wr_en), .clk(buf_clk), .*);
rvdffs #(.WIDTH(1)) slvbuf_errorff (.din(slvbuf_error_in), .dout(slvbuf_error), .en(slvbuf_error_en), .clk(ahbm_clk), .*);
rvdffsc #(.WIDTH(1)) buf_cmd_doneff (.din(1'b1), .en(cmd_done), .dout(cmd_doneQ), .clear(cmd_done_rst), .clk(ahbm_clk), .*);
rvdffs #(.WIDTH(3)) buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en), .clk(ahbm_clk), .*);
rvdff #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(ahbm_clk), .*);
rvdff #(.WIDTH(2)) htrans_ff (.din(ahb_htrans[1:0]), .dout(ahb_htrans_q[1:0]), .clk(ahbm_clk), .*);
rvdff #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(ahbm_addr_clk), .*);
rvdff #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(ahbm_clk), .*);
rvdff #(.WIDTH(64)) hrdata_ff (.din(ahb_hrdata[63:0]), .dout(ahb_hrdata_q[63:0]), .clk(ahbm_data_clk), .*);
// Clock headers // Clock headers
// clock enables for ahbm addr/data // clock enables for ahbm addr/data
@ -445,10 +458,6 @@ module axi4_to_ahb #(parameter TAG = 1) (
assign ahbm_addr_clken = bus_clk_en & ((ahb_hready & ahb_htrans[1]) | clk_override); assign ahbm_addr_clken = bus_clk_en & ((ahb_hready & ahb_htrans[1]) | clk_override);
assign ahbm_data_clken = bus_clk_en & ((buf_state != IDLE) | clk_override); assign ahbm_data_clken = bus_clk_en & ((buf_state != IDLE) | clk_override);
rvclkhdr buf_cgc (.en(buf_clken), .l1clk(buf_clk), .*);
rvclkhdr ahbm_cgc (.en(bus_clk_en), .l1clk(ahbm_clk), .*);
rvclkhdr ahbm_addr_cgc (.en(ahbm_addr_clken), .l1clk(ahbm_addr_clk), .*);
rvclkhdr ahbm_data_cgc (.en(ahbm_data_clken), .l1clk(ahbm_data_clk), .*);
`ifdef ASSERT_ON `ifdef ASSERT_ON
property ahb_trxn_aligned; property ahb_trxn_aligned;

75
design/lib/beh_lib.sv
View File

@ -72,6 +72,73 @@ module rvdffsc #( parameter WIDTH=1 )
endmodule endmodule
// versions with clock enables .clken to assist in RV_FPGA_OPTIMIZE
module rvdff_fpga #( parameter WIDTH=1 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);
`else
rvdff #(WIDTH) dff (.*);
`endif
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs_fpga #( parameter WIDTH=1 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*);
`else
rvdffs #(WIDTH) dffs (.*);
`endif
endmodule
// rvdff with en and clear
module rvdffsc_fpga #( parameter WIDTH=1 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);
`else
rvdffsc #(WIDTH) dffsc (.*);
`endif
endmodule
module `TEC_RV_ICG module `TEC_RV_ICG
( (
input logic TE, E, CP, input logic TE, E, CP,
@ -97,6 +164,7 @@ module `TEC_RV_ICG
endmodule endmodule
`ifndef RV_FPGA_OPTIMIZE
module rvclkhdr module rvclkhdr
( (
input logic en, input logic en,
@ -110,7 +178,8 @@ module rvclkhdr
`TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk)); `TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
endmodule endmodule // rvclkhdr
`endif
module rvoclkhdr module rvoclkhdr
( (
@ -131,7 +200,7 @@ module rvoclkhdr
endmodule endmodule
module rvdffe #( parameter WIDTH=1 ) module rvdffe #( parameter WIDTH=1, parameter OVERRIDE=0 )
( (
input logic [WIDTH-1:0] din, input logic [WIDTH-1:0] din,
input logic en, input logic en,
@ -145,7 +214,7 @@ module rvdffe #( parameter WIDTH=1 )
`ifndef PHYSICAL `ifndef PHYSICAL
if (WIDTH >= 8) begin: genblock if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif `endif
`ifdef RV_FPGA_OPTIMIZE `ifdef RV_FPGA_OPTIMIZE

12
design/lsu/lsu.sv
View File

@ -260,12 +260,13 @@ module lsu
logic lsu_c2_dc3_clk, lsu_c2_dc4_clk, lsu_c2_dc5_clk; logic lsu_c2_dc3_clk, lsu_c2_dc4_clk, lsu_c2_dc5_clk;
logic lsu_freeze_c1_dc2_clk, lsu_freeze_c1_dc3_clk; logic lsu_freeze_c1_dc2_clk, lsu_freeze_c1_dc3_clk;
logic lsu_freeze_c1_dc1_clken, lsu_freeze_c1_dc2_clken, lsu_freeze_c1_dc3_clken; logic lsu_freeze_c1_dc1_clken, lsu_freeze_c1_dc2_clken, lsu_freeze_c1_dc3_clken;
logic lsu_freeze_c2_dc1_clken, lsu_freeze_c2_dc2_clken, lsu_freeze_c2_dc3_clken, lsu_freeze_c2_dc4_clken;
logic lsu_store_c1_dc1_clken, lsu_store_c1_dc2_clken, lsu_store_c1_dc3_clken, lsu_store_c1_dc4_clk, lsu_store_c1_dc5_clk; logic lsu_store_c1_dc1_clken, lsu_store_c1_dc2_clken, lsu_store_c1_dc3_clken, lsu_store_c1_dc4_clk, lsu_store_c1_dc5_clk;
logic lsu_freeze_c2_dc1_clk, lsu_freeze_c2_dc2_clk, lsu_freeze_c2_dc3_clk, lsu_freeze_c2_dc4_clk; logic lsu_freeze_c2_dc1_clk, lsu_freeze_c2_dc2_clk, lsu_freeze_c2_dc3_clk, lsu_freeze_c2_dc4_clk;
logic lsu_stbuf_c1_clk; logic lsu_stbuf_c1_clk;
logic lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk; logic lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
logic lsu_dccm_c1_dc3_clk, lsu_pic_c1_dc3_clken; logic lsu_dccm_c1_dc3_clk, lsu_dccm_c1_dc3_clken, lsu_pic_c1_dc3_clken;
logic lsu_busm_clk; logic lsu_busm_clk;
logic lsu_free_c2_clk; logic lsu_free_c2_clk;
@ -359,10 +360,11 @@ module lsu
//Flops //Flops
//rvdffs #(1) lsu_i0_valid_dc1ff (.*, .din(dec_i0_lsu_decode_d), .dout(lsu_i0_valid_dc1), .en(~lsu_freeze_dc3)); //rvdffs #(1) lsu_i0_valid_dc1ff (.*, .din(dec_i0_lsu_decode_d), .dout(lsu_i0_valid_dc1), .en(~lsu_freeze_dc3));
rvdff #(1) lsu_i0_valid_dc1ff (.*, .din(dec_i0_lsu_decode_d), .dout(lsu_i0_valid_dc1), .clk(lsu_freeze_c2_dc1_clk)); rvdff_fpga #(1) lsu_i0_valid_dc1ff (.*, .din(dec_i0_lsu_decode_d), .dout(lsu_i0_valid_dc1), .clk(lsu_freeze_c2_dc1_clk), .clken(lsu_freeze_c2_dc1_clken), .rawclk(clk));
rvdff #(1) lsu_i0_valid_dc2ff (.*, .din(lsu_i0_valid_dc1), .dout(lsu_i0_valid_dc2), .clk(lsu_freeze_c2_dc2_clk)); rvdff_fpga #(1) lsu_i0_valid_dc2ff (.*, .din(lsu_i0_valid_dc1), .dout(lsu_i0_valid_dc2), .clk(lsu_freeze_c2_dc2_clk), .clken(lsu_freeze_c2_dc2_clken), .rawclk(clk));
rvdff #(1) lsu_i0_valid_dc3ff (.*, .din(lsu_i0_valid_dc2), .dout(lsu_i0_valid_dc3), .clk(lsu_freeze_c2_dc3_clk)); rvdff_fpga #(1) lsu_i0_valid_dc3ff (.*, .din(lsu_i0_valid_dc2), .dout(lsu_i0_valid_dc3), .clk(lsu_freeze_c2_dc3_clk), .clken(lsu_freeze_c2_dc3_clken), .rawclk(clk));
rvdff #(1) lsu_i0_valid_dc4ff (.*, .din(lsu_i0_valid_dc3), .dout(lsu_i0_valid_dc4), .clk(lsu_freeze_c2_dc4_clk)); rvdff_fpga #(1) lsu_i0_valid_dc4ff (.*, .din(lsu_i0_valid_dc3), .dout(lsu_i0_valid_dc4), .clk(lsu_freeze_c2_dc4_clk), .clken(lsu_freeze_c2_dc4_clken), .rawclk(clk));
rvdff #(1) lsu_i0_valid_dc5ff (.*, .din(lsu_i0_valid_dc4), .dout(lsu_i0_valid_dc5), .clk(lsu_c2_dc5_clk)); rvdff #(1) lsu_i0_valid_dc5ff (.*, .din(lsu_i0_valid_dc4), .dout(lsu_i0_valid_dc5), .clk(lsu_c2_dc5_clk));
rvdff #(1) lsu_single_ecc_err_dc4(.*, .din(lsu_single_ecc_error_dc3), .dout(lsu_single_ecc_error_dc4), .clk(lsu_c2_dc4_clk)); rvdff #(1) lsu_single_ecc_err_dc4(.*, .din(lsu_single_ecc_error_dc3), .dout(lsu_single_ecc_error_dc4), .clk(lsu_c2_dc4_clk));
rvdff #(1) lsu_single_ecc_err_dc5(.*, .din(lsu_single_ecc_error_dc4), .dout(lsu_single_ecc_error_dc5), .clk(lsu_c2_dc5_clk)); rvdff #(1) lsu_single_ecc_err_dc5(.*, .din(lsu_single_ecc_error_dc4), .dout(lsu_single_ecc_error_dc5), .clk(lsu_c2_dc5_clk));

8
design/lsu/lsu_addrcheck.sv
View File

@ -27,7 +27,10 @@ module lsu_addrcheck
( (
input logic lsu_freeze_c2_dc2_clk, // clock input logic lsu_freeze_c2_dc2_clk, // clock
input logic lsu_freeze_c2_dc3_clk, input logic lsu_freeze_c2_dc3_clk,
input logic lsu_freeze_c2_dc2_clken,
input logic lsu_freeze_c2_dc3_clken,
input logic rst_l, // reset input logic rst_l, // reset
input logic clk,
input logic [31:0] start_addr_dc1, // start address for lsu input logic [31:0] start_addr_dc1, // start address for lsu
input logic [31:0] end_addr_dc1, // end address for lsu input logic [31:0] end_addr_dc1, // end address for lsu
@ -177,8 +180,9 @@ module lsu_addrcheck
assign misaligned_fault_dc1 = ((start_addr_dc1[31:28] != end_addr_dc1[31:28]) | assign misaligned_fault_dc1 = ((start_addr_dc1[31:28] != end_addr_dc1[31:28]) |
(is_sideeffects_dc1 & ~is_aligned_dc1)) & addr_external_dc1 & lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma; (is_sideeffects_dc1 & ~is_aligned_dc1)) & addr_external_dc1 & lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma;
rvdff #(.WIDTH(1)) is_sideeffects_dc2ff (.din(is_sideeffects_dc1), .dout(is_sideeffects_dc2), .clk(lsu_freeze_c2_dc2_clk), .*); rvdff_fpga #(.WIDTH(1)) is_sideeffects_dc2ff (.din(is_sideeffects_dc1), .dout(is_sideeffects_dc2), .clk(lsu_freeze_c2_dc2_clk), .clken(lsu_freeze_c2_dc2_clken), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) is_sideeffects_dc3ff (.din(is_sideeffects_dc2), .dout(is_sideeffects_dc3), .clk(lsu_freeze_c2_dc3_clk), .*); rvdff_fpga #(.WIDTH(1)) is_sideeffects_dc3ff (.din(is_sideeffects_dc2), .dout(is_sideeffects_dc3), .clk(lsu_freeze_c2_dc3_clk), .clken(lsu_freeze_c2_dc3_clken), .rawclk(clk), .*);
endmodule // lsu_addrcheck endmodule // lsu_addrcheck

49
design/lsu/lsu_bus_buffer.sv
View File

@ -58,6 +58,7 @@ module lsu_bus_buffer
input logic lsu_freeze_c1_dc3_clk, input logic lsu_freeze_c1_dc3_clk,
input logic lsu_freeze_c2_dc2_clk, input logic lsu_freeze_c2_dc2_clk,
input logic lsu_freeze_c2_dc3_clk, input logic lsu_freeze_c2_dc3_clk,
input logic lsu_freeze_c2_dc3_clken,
input logic lsu_bus_ibuf_c1_clk, input logic lsu_bus_ibuf_c1_clk,
input logic lsu_bus_obuf_c1_clk, input logic lsu_bus_obuf_c1_clk,
input logic lsu_bus_buf_c1_clk, input logic lsu_bus_buf_c1_clk,
@ -527,10 +528,28 @@ module lsu_bus_buffer
assign obuf_merge_en = (CmdPtr0 != CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state[CmdPtr0] == CMD) & (buf_state[CmdPtr1] == CMD) & ~buf_cmd_state_bus_en[CmdPtr0] & ~buf_sideeffect[CmdPtr0] & assign obuf_merge_en = (CmdPtr0 != CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state[CmdPtr0] == CMD) & (buf_state[CmdPtr1] == CMD) & ~buf_cmd_state_bus_en[CmdPtr0] & ~buf_sideeffect[CmdPtr0] &
(~buf_write[CmdPtr0] & buf_dual[CmdPtr0] & ~buf_dualhi[CmdPtr0] & buf_samedw[CmdPtr0]); // CmdPtr0/CmdPtr1 are for same load which is within a DW (~buf_write[CmdPtr0] & buf_dual[CmdPtr0] & ~buf_dualhi[CmdPtr0] & buf_samedw[CmdPtr0]); // CmdPtr0/CmdPtr1 are for same load which is within a DW
rvdff #(.WIDTH(1)) obuf_wren_ff (.din(obuf_wr_en), .dout(obuf_wr_enQ), .clk(lsu_busm_clk), .*); rvdff_fpga #(1) obuf_wren_ff (.din(obuf_wr_en), .dout(obuf_wr_enQ), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) obuf_cmd_done_ff (.din(obuf_cmd_done_in), .dout(obuf_cmd_done), .clk(lsu_busm_clk), .*); rvdff_fpga #(1) obuf_cmd_done_ff (.din(obuf_cmd_done_in), .dout(obuf_cmd_done), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) obuf_data_done_ff (.din(obuf_data_done_in), .dout(obuf_data_done), .clk(lsu_busm_clk), .*); rvdff_fpga #(1) obuf_data_done_ff (.din(obuf_data_done_in), .dout(obuf_data_done), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdffsc #(.WIDTH(1)) obuf_valid_ff (.din(1'b1), .dout(obuf_valid), .en(obuf_wr_en), .clear(obuf_rst), .clk(lsu_busm_clk), .*); rvdffsc_fpga #(1) obuf_valid_ff (.din(1'b1), .dout(obuf_valid), .clear(obuf_rst), .en(obuf_wr_en), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(TIMER_LOG2) obuf_timerff (.din(obuf_wr_timer_in), .dout(obuf_wr_timer), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_awvalid_ff (.din(lsu_axi_awvalid), .dout(lsu_axi_awvalid_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_awready_ff (.din(lsu_axi_awready), .dout(lsu_axi_awready_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_wvalid_ff (.din(lsu_axi_wvalid), .dout(lsu_axi_wvalid_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_wready_ff (.din(lsu_axi_wready), .dout(lsu_axi_wready_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_arvalid_ff (.din(lsu_axi_arvalid), .dout(lsu_axi_arvalid_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_arready_ff (.din(lsu_axi_arready), .dout(lsu_axi_arready_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_bvalid_ff (.din(lsu_axi_bvalid), .dout(lsu_axi_bvalid_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_bready_ff (.din(lsu_axi_bready), .dout(lsu_axi_bready_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(2) lsu_axi_bresp_ff (.din(lsu_axi_bresp[1:0]), .dout(lsu_axi_bresp_q[1:0]), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(LSU_BUS_TAG) lsu_axi_bid_ff (.din(lsu_axi_bid[LSU_BUS_TAG-1:0]), .dout(lsu_axi_bid_q[LSU_BUS_TAG-1:0]), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_rvalid_ff (.din(lsu_axi_rvalid), .dout(lsu_axi_rvalid_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(1) lsu_axi_rready_ff (.din(lsu_axi_rready), .dout(lsu_axi_rready_q), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(2) lsu_axi_rresp_ff (.din(lsu_axi_rresp[1:0]), .dout(lsu_axi_rresp_q[1:0]), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdff_fpga #(LSU_BUS_TAG) lsu_axi_rid_ff (.din(lsu_axi_rid[LSU_BUS_TAG-1:0]), .dout(lsu_axi_rid_q[LSU_BUS_TAG-1:0]), .clk(lsu_busm_clk), .clken(lsu_bus_clk_en), .rawclk(clk), .*);
rvdffs #(.WIDTH(LSU_BUS_TAG)) obuf_tag0ff (.din(obuf_tag0_in), .dout(obuf_tag0), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*); rvdffs #(.WIDTH(LSU_BUS_TAG)) obuf_tag0ff (.din(obuf_tag0_in), .dout(obuf_tag0), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*);
rvdffs #(.WIDTH(LSU_BUS_TAG)) obuf_tag1ff (.din(obuf_tag1_in), .dout(obuf_tag1), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*); rvdffs #(.WIDTH(LSU_BUS_TAG)) obuf_tag1ff (.din(obuf_tag1_in), .dout(obuf_tag1), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*);
rvdffs #(.WIDTH(1)) obuf_mergeff (.din(obuf_merge_in), .dout(obuf_merge), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*); rvdffs #(.WIDTH(1)) obuf_mergeff (.din(obuf_merge_in), .dout(obuf_merge), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*);
@ -540,7 +559,6 @@ module lsu_bus_buffer
rvdffe #(.WIDTH(32)) obuf_addrff (.din(obuf_addr_in[31:0]), .dout(obuf_addr), .en(obuf_wr_en), .*); rvdffe #(.WIDTH(32)) obuf_addrff (.din(obuf_addr_in[31:0]), .dout(obuf_addr), .en(obuf_wr_en), .*);
rvdffs #(.WIDTH(8)) obuf_byteenff (.din(obuf_byteen_in[7:0]), .dout(obuf_byteen), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*); rvdffs #(.WIDTH(8)) obuf_byteenff (.din(obuf_byteen_in[7:0]), .dout(obuf_byteen), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .*);
rvdffe #(.WIDTH(64)) obuf_dataff (.din(obuf_data_in[63:0]), .dout(obuf_data), .en(obuf_wr_en), .*); rvdffe #(.WIDTH(64)) obuf_dataff (.din(obuf_data_in[63:0]), .dout(obuf_data), .en(obuf_wr_en), .*);
rvdff #(.WIDTH(TIMER_LOG2)) obuf_timerff (.din(obuf_wr_timer_in), .dout(obuf_wr_timer), .clk(lsu_busm_clk), .*);
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// Output buffer logic ends here // Output buffer logic ends here
@ -872,24 +890,8 @@ module lsu_bus_buffer
assign lsu_pmu_bus_error = ld_bus_error_dc3 | lsu_imprecise_error_load_any | lsu_imprecise_error_store_any; assign lsu_pmu_bus_error = ld_bus_error_dc3 | lsu_imprecise_error_load_any | lsu_imprecise_error_store_any;
assign lsu_pmu_bus_busy = (lsu_axi_awvalid_q & ~lsu_axi_awready_q) | (lsu_axi_wvalid_q & ~lsu_axi_wready_q) | (lsu_axi_arvalid_q & ~lsu_axi_arready_q); assign lsu_pmu_bus_busy = (lsu_axi_awvalid_q & ~lsu_axi_awready_q) | (lsu_axi_wvalid_q & ~lsu_axi_wready_q) | (lsu_axi_arvalid_q & ~lsu_axi_arready_q);
rvdff #(.WIDTH(1)) lsu_axi_awvalid_ff (.din(lsu_axi_awvalid), .dout(lsu_axi_awvalid_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_awready_ff (.din(lsu_axi_awready), .dout(lsu_axi_awready_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_wvalid_ff (.din(lsu_axi_wvalid), .dout(lsu_axi_wvalid_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_wready_ff (.din(lsu_axi_wready), .dout(lsu_axi_wready_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_arvalid_ff (.din(lsu_axi_arvalid), .dout(lsu_axi_arvalid_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_arready_ff (.din(lsu_axi_arready), .dout(lsu_axi_arready_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_bvalid_ff (.din(lsu_axi_bvalid), .dout(lsu_axi_bvalid_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_bready_ff (.din(lsu_axi_bready), .dout(lsu_axi_bready_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(2)) lsu_axi_bresp_ff (.din(lsu_axi_bresp[1:0]), .dout(lsu_axi_bresp_q[1:0]), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(LSU_BUS_TAG)) lsu_axi_bid_ff (.din(lsu_axi_bid[LSU_BUS_TAG-1:0]), .dout(lsu_axi_bid_q[LSU_BUS_TAG-1:0]), .clk(lsu_busm_clk), .*);
rvdffe #(.WIDTH(64)) lsu_axi_rdata_ff (.din(lsu_axi_rdata[63:0]), .dout(lsu_axi_rdata_q[63:0]), .en(lsu_axi_rvalid & lsu_bus_clk_en), .*); rvdffe #(.WIDTH(64)) lsu_axi_rdata_ff (.din(lsu_axi_rdata[63:0]), .dout(lsu_axi_rdata_q[63:0]), .en(lsu_axi_rvalid & lsu_bus_clk_en), .*);
rvdff #(.WIDTH(1)) lsu_axi_rvalid_ff (.din(lsu_axi_rvalid), .dout(lsu_axi_rvalid_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(1)) lsu_axi_rready_ff (.din(lsu_axi_rready), .dout(lsu_axi_rready_q), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(2)) lsu_axi_rresp_ff (.din(lsu_axi_rresp[1:0]), .dout(lsu_axi_rresp_q[1:0]), .clk(lsu_busm_clk), .*);
rvdff #(.WIDTH(LSU_BUS_TAG)) lsu_axi_rid_ff (.din(lsu_axi_rid[LSU_BUS_TAG-1:0]), .dout(lsu_axi_rid_q[LSU_BUS_TAG-1:0]), .clk(lsu_busm_clk), .*);
// General flops // General flops
rvdffsc #(.WIDTH(1)) ld_freezeff (.din(1'b1), .dout(ld_freeze_dc3), .en(ld_freeze_en), .clear(ld_freeze_rst), .clk(lsu_free_c2_clk), .*); rvdffsc #(.WIDTH(1)) ld_freezeff (.din(1'b1), .dout(ld_freeze_dc3), .en(ld_freeze_en), .clear(ld_freeze_rst), .clk(lsu_free_c2_clk), .*);
rvdffs #(.WIDTH(DEPTH_LOG2)) lsu_FreezePtrff (.din(WrPtr0_dc3), .dout(FreezePtr), .en(FreezePtrEn), .clk(lsu_free_c2_clk), .*); rvdffs #(.WIDTH(DEPTH_LOG2)) lsu_FreezePtrff (.din(WrPtr0_dc3), .dout(FreezePtr), .en(FreezePtrEn), .clk(lsu_free_c2_clk), .*);
@ -905,7 +907,10 @@ module lsu_bus_buffer
rvdff #(.WIDTH(1)) lsu_busreq_dc4ff (.din(lsu_busreq_dc3 & ~flush_dc4), .dout(lsu_busreq_dc4), .clk(lsu_c2_dc4_clk), .*); rvdff #(.WIDTH(1)) lsu_busreq_dc4ff (.din(lsu_busreq_dc3 & ~flush_dc4), .dout(lsu_busreq_dc4), .clk(lsu_c2_dc4_clk), .*);
rvdff #(.WIDTH(1)) lsu_busreq_dc5ff (.din(lsu_busreq_dc4 & ~flush_dc5), .dout(lsu_busreq_dc5), .clk(lsu_c2_dc5_clk), .*); rvdff #(.WIDTH(1)) lsu_busreq_dc5ff (.din(lsu_busreq_dc4 & ~flush_dc5), .dout(lsu_busreq_dc5), .clk(lsu_c2_dc5_clk), .*);
rvdff #(.WIDTH(1)) dec_nonblock_load_freeze_dc3ff (.din(dec_nonblock_load_freeze_dc2), .dout(dec_nonblock_load_freeze_dc3), .clk(lsu_freeze_c2_dc3_clk), .*); rvdff_fpga #(.WIDTH(1)) dec_nonblock_load_freeze_dc3ff (.din(dec_nonblock_load_freeze_dc2), .dout(dec_nonblock_load_freeze_dc3), .clk(lsu_freeze_c2_dc3_clk), .clken(lsu_freeze_c2_dc3_clken), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_dc4ff (.din(lsu_nonblock_load_valid_dc3), .dout(lsu_nonblock_load_valid_dc4), .clk(lsu_c2_dc4_clk), .*); rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_dc4ff (.din(lsu_nonblock_load_valid_dc3), .dout(lsu_nonblock_load_valid_dc4), .clk(lsu_c2_dc4_clk), .*);
rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_dc5ff (.din(lsu_nonblock_load_valid_dc4), .dout(lsu_nonblock_load_valid_dc5), .clk(lsu_c2_dc5_clk), .*); rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_dc5ff (.din(lsu_nonblock_load_valid_dc4), .dout(lsu_nonblock_load_valid_dc5), .clk(lsu_c2_dc5_clk), .*);

16
design/lsu/lsu_bus_intf.sv
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@ -44,6 +44,10 @@ module lsu_bus_intf
input logic lsu_freeze_c1_dc3_clk, input logic lsu_freeze_c1_dc3_clk,
input logic lsu_freeze_c2_dc2_clk, input logic lsu_freeze_c2_dc2_clk,
input logic lsu_freeze_c2_dc3_clk, input logic lsu_freeze_c2_dc3_clk,
input logic lsu_freeze_c1_dc2_clken,
input logic lsu_freeze_c1_dc3_clken,
input logic lsu_freeze_c2_dc2_clken,
input logic lsu_freeze_c2_dc3_clken,
input logic lsu_bus_ibuf_c1_clk, input logic lsu_bus_ibuf_c1_clk,
input logic lsu_bus_obuf_c1_clk, input logic lsu_bus_obuf_c1_clk,
input logic lsu_bus_buf_c1_clk, input logic lsu_bus_buf_c1_clk,
@ -383,19 +387,21 @@ module lsu_bus_intf
assign bus_read_data_dc3[31:0] = ld_full_hit_dc3 ? ld_fwddata_dc3[31:0] : ld_bus_data_dc3[31:0]; assign bus_read_data_dc3[31:0] = ld_full_hit_dc3 ? ld_fwddata_dc3[31:0] : ld_bus_data_dc3[31:0];
// Fifo flops // Fifo flops
rvdff #(.WIDTH(1)) lsu_full_hit_dc3ff (.din(ld_full_hit_dc2), .dout(ld_full_hit_dc3), .clk(lsu_freeze_c2_dc3_clk), .*);
rvdff #(.WIDTH(32)) lsu_fwddata_dc3ff (.din(ld_fwddata_dc2[31:0]), .dout(ld_fwddata_dc3[31:0]), .clk(lsu_c1_dc3_clk), .*);
rvdff #(.WIDTH(1)) clken_ff (.din(lsu_bus_clk_en), .dout(lsu_bus_clk_en_q), .clk(free_clk), .*); rvdff #(.WIDTH(1)) clken_ff (.din(lsu_bus_clk_en), .dout(lsu_bus_clk_en_q), .clk(free_clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc2ff (.din(ldst_dual_dc1), .dout(ldst_dual_dc2), .clk(lsu_freeze_c1_dc2_clk), .*); rvdff_fpga #(.WIDTH(1)) ldst_dual_dc2ff (.din(ldst_dual_dc1), .dout(ldst_dual_dc2), .clk(lsu_freeze_c1_dc2_clk), .clken(lsu_freeze_c1_dc2_clken), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc3ff (.din(ldst_dual_dc2), .dout(ldst_dual_dc3), .clk(lsu_freeze_c1_dc3_clk), .*); rvdff_fpga #(.WIDTH(1)) lsu_full_hit_dc3ff (.din(ld_full_hit_dc2), .dout(ld_full_hit_dc3), .clk(lsu_freeze_c2_dc3_clk), .clken(lsu_freeze_c2_dc3_clken), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(1)) ldst_dual_dc3ff (.din(ldst_dual_dc2), .dout(ldst_dual_dc3), .clk(lsu_freeze_c1_dc3_clk), .clken(lsu_freeze_c1_dc3_clken), .rawclk(clk), .*);
rvdff_fpga #(4) lsu_byten_dc3ff (.din(ldst_byteen_dc2[3:0]), .dout(ldst_byteen_dc3[3:0]), .clk(lsu_freeze_c1_dc3_clk), .clken(lsu_freeze_c1_dc3_clken), .rawclk(clk), .*);
rvdff #(.WIDTH(32)) lsu_fwddata_dc3ff (.din(ld_fwddata_dc2[31:0]), .dout(ld_fwddata_dc3[31:0]), .clk(lsu_c1_dc3_clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc4ff (.din(ldst_dual_dc3), .dout(ldst_dual_dc4), .clk(lsu_c1_dc4_clk), .*); rvdff #(.WIDTH(1)) ldst_dual_dc4ff (.din(ldst_dual_dc3), .dout(ldst_dual_dc4), .clk(lsu_c1_dc4_clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc5ff (.din(ldst_dual_dc4), .dout(ldst_dual_dc5), .clk(lsu_c1_dc5_clk), .*); rvdff #(.WIDTH(1)) ldst_dual_dc5ff (.din(ldst_dual_dc4), .dout(ldst_dual_dc5), .clk(lsu_c1_dc5_clk), .*);
rvdff #(.WIDTH(1)) is_sideeffects_dc4ff (.din(is_sideeffects_dc3), .dout(is_sideeffects_dc4), .clk(lsu_c1_dc4_clk), .*); rvdff #(.WIDTH(1)) is_sideeffects_dc4ff (.din(is_sideeffects_dc3), .dout(is_sideeffects_dc4), .clk(lsu_c1_dc4_clk), .*);
rvdff #(.WIDTH(1)) is_sideeffects_dc5ff (.din(is_sideeffects_dc4), .dout(is_sideeffects_dc5), .clk(lsu_c1_dc5_clk), .*); rvdff #(.WIDTH(1)) is_sideeffects_dc5ff (.din(is_sideeffects_dc4), .dout(is_sideeffects_dc5), .clk(lsu_c1_dc5_clk), .*);
rvdff #(4) lsu_byten_dc3ff (.*, .din(ldst_byteen_dc2[3:0]), .dout(ldst_byteen_dc3[3:0]), .clk(lsu_freeze_c1_dc3_clk));
rvdff #(4) lsu_byten_dc4ff (.*, .din(ldst_byteen_dc3[3:0]), .dout(ldst_byteen_dc4[3:0]), .clk(lsu_c1_dc4_clk)); rvdff #(4) lsu_byten_dc4ff (.*, .din(ldst_byteen_dc3[3:0]), .dout(ldst_byteen_dc4[3:0]), .clk(lsu_c1_dc4_clk));
rvdff #(4) lsu_byten_dc5ff (.*, .din(ldst_byteen_dc4[3:0]), .dout(ldst_byteen_dc5[3:0]), .clk(lsu_c1_dc5_clk)); rvdff #(4) lsu_byten_dc5ff (.*, .din(ldst_byteen_dc4[3:0]), .dout(ldst_byteen_dc5[3:0]), .clk(lsu_c1_dc5_clk));

55
design/lsu/lsu_clkdomain.sv
View File

@ -84,7 +84,14 @@ module lsu_clkdomain
output logic lsu_freeze_c2_dc3_clk, output logic lsu_freeze_c2_dc3_clk,
output logic lsu_freeze_c2_dc4_clk, output logic lsu_freeze_c2_dc4_clk,
output logic lsu_freeze_c2_dc1_clken,
output logic lsu_freeze_c2_dc2_clken,
output logic lsu_freeze_c2_dc3_clken,
output logic lsu_freeze_c2_dc4_clken,
output logic lsu_dccm_c1_dc3_clk, // dccm clock output logic lsu_dccm_c1_dc3_clk, // dccm clock
output logic lsu_dccm_c1_dc3_clken,
output logic lsu_pic_c1_dc3_clken, // pic clock enable output logic lsu_pic_c1_dc3_clken, // pic clock enable
output logic lsu_stbuf_c1_clk, output logic lsu_stbuf_c1_clk,
@ -104,13 +111,12 @@ module lsu_clkdomain
logic lsu_store_c1_dc4_clken, lsu_store_c1_dc5_clken; logic lsu_store_c1_dc4_clken, lsu_store_c1_dc5_clken;
logic lsu_freeze_c1_dc4_clken; logic lsu_freeze_c1_dc4_clken;
logic lsu_freeze_c2_dc1_clken, lsu_freeze_c2_dc2_clken, lsu_freeze_c2_dc3_clken, lsu_freeze_c2_dc4_clken;
logic lsu_freeze_c1_dc1_clken_q, lsu_freeze_c1_dc2_clken_q, lsu_freeze_c1_dc3_clken_q, lsu_freeze_c1_dc4_clken_q; logic lsu_freeze_c1_dc1_clken_q, lsu_freeze_c1_dc2_clken_q, lsu_freeze_c1_dc3_clken_q, lsu_freeze_c1_dc4_clken_q;
logic lsu_stbuf_c1_clken; logic lsu_stbuf_c1_clken;
logic lsu_bus_ibuf_c1_clken, lsu_bus_obuf_c1_clken, lsu_bus_buf_c1_clken; logic lsu_bus_ibuf_c1_clken, lsu_bus_obuf_c1_clken, lsu_bus_buf_c1_clken;
logic lsu_dccm_c1_dc3_clken;
logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken; logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
logic lsu_bus_valid_clken; logic lsu_bus_valid_clken;
@ -168,10 +174,10 @@ module lsu_clkdomain
rvdff #(1) lsu_c1_dc4_clkenff (.din(lsu_c1_dc4_clken), .dout(lsu_c1_dc4_clken_q), .clk(lsu_free_c2_clk), .*); rvdff #(1) lsu_c1_dc4_clkenff (.din(lsu_c1_dc4_clken), .dout(lsu_c1_dc4_clken_q), .clk(lsu_free_c2_clk), .*);
rvdff #(1) lsu_c1_dc5_clkenff (.din(lsu_c1_dc5_clken), .dout(lsu_c1_dc5_clken_q), .clk(lsu_free_c2_clk), .*); rvdff #(1) lsu_c1_dc5_clkenff (.din(lsu_c1_dc5_clken), .dout(lsu_c1_dc5_clken_q), .clk(lsu_free_c2_clk), .*);
rvdff #(1) lsu_freeze_c1_dc1_clkenff (.din(lsu_freeze_c1_dc1_clken), .dout(lsu_freeze_c1_dc1_clken_q), .clk(lsu_freeze_c2_dc1_clk), .*); rvdff_fpga #(1) lsu_freeze_c1_dc1_clkenff (.din(lsu_freeze_c1_dc1_clken), .dout(lsu_freeze_c1_dc1_clken_q), .clk(lsu_freeze_c2_dc1_clk), .clken(lsu_freeze_c2_dc1_clken), .rawclk(clk), .*);
rvdff #(1) lsu_freeze_c1_dc2_clkenff (.din(lsu_freeze_c1_dc2_clken), .dout(lsu_freeze_c1_dc2_clken_q), .clk(lsu_freeze_c2_dc2_clk), .*); rvdff_fpga #(1) lsu_freeze_c1_dc2_clkenff (.din(lsu_freeze_c1_dc2_clken), .dout(lsu_freeze_c1_dc2_clken_q), .clk(lsu_freeze_c2_dc2_clk), .clken(lsu_freeze_c2_dc2_clken), .rawclk(clk), .*);
rvdff #(1) lsu_freeze_c1_dc3_clkenff (.din(lsu_freeze_c1_dc3_clken), .dout(lsu_freeze_c1_dc3_clken_q), .clk(lsu_freeze_c2_dc3_clk), .*); rvdff_fpga #(1) lsu_freeze_c1_dc3_clkenff (.din(lsu_freeze_c1_dc3_clken), .dout(lsu_freeze_c1_dc3_clken_q), .clk(lsu_freeze_c2_dc3_clk), .clken(lsu_freeze_c2_dc3_clken), .rawclk(clk), .*);
rvdff #(1) lsu_freeze_c1_dc4_clkenff (.din(lsu_freeze_c1_dc4_clken), .dout(lsu_freeze_c1_dc4_clken_q), .clk(lsu_freeze_c2_dc4_clk), .*); rvdff_fpga #(1) lsu_freeze_c1_dc4_clkenff (.din(lsu_freeze_c1_dc4_clken), .dout(lsu_freeze_c1_dc4_clken_q), .clk(lsu_freeze_c2_dc4_clk), .clken(lsu_freeze_c2_dc4_clken), .rawclk(clk), .*);
// Clock Headers // Clock Headers
rvoclkhdr lsu_c1dc3_cgc ( .en(lsu_c1_dc3_clken), .l1clk(lsu_c1_dc3_clk), .* ); rvoclkhdr lsu_c1dc3_cgc ( .en(lsu_c1_dc3_clken), .l1clk(lsu_c1_dc3_clk), .* );
@ -182,32 +188,41 @@ module lsu_clkdomain
rvoclkhdr lsu_c2dc4_cgc ( .en(lsu_c2_dc4_clken), .l1clk(lsu_c2_dc4_clk), .* ); rvoclkhdr lsu_c2dc4_cgc ( .en(lsu_c2_dc4_clken), .l1clk(lsu_c2_dc4_clk), .* );
rvoclkhdr lsu_c2dc5_cgc ( .en(lsu_c2_dc5_clken), .l1clk(lsu_c2_dc5_clk), .* ); rvoclkhdr lsu_c2dc5_cgc ( .en(lsu_c2_dc5_clken), .l1clk(lsu_c2_dc5_clk), .* );
// rvclkhdr lsu_store_c1dc1_cgc (.en(lsu_store_c1_dc1_clken), .l1clk(lsu_store_c1_dc1_clk), .*);
// rvclkhdr lsu_store_c1dc2_cgc (.en(lsu_store_c1_dc2_clken), .l1clk(lsu_store_c1_dc2_clk), .*);
// rvclkhdr lsu_store_c1dc3_cgc (.en(lsu_store_c1_dc3_clken), .l1clk(lsu_store_c1_dc3_clk), .*);
rvoclkhdr lsu_store_c1dc4_cgc (.en(lsu_store_c1_dc4_clken), .l1clk(lsu_store_c1_dc4_clk), .*); rvoclkhdr lsu_store_c1dc4_cgc (.en(lsu_store_c1_dc4_clken), .l1clk(lsu_store_c1_dc4_clk), .*);
rvoclkhdr lsu_store_c1dc5_cgc (.en(lsu_store_c1_dc5_clken), .l1clk(lsu_store_c1_dc5_clk), .*); rvoclkhdr lsu_store_c1dc5_cgc (.en(lsu_store_c1_dc5_clken), .l1clk(lsu_store_c1_dc5_clk), .*);
// rvclkhdr lsu_freeze_c1dc1_cgc ( .en(lsu_freeze_c1_dc1_clken), .l1clk(lsu_freeze_c1_dc1_clk), .* ); `ifdef RV_FPGA_OPTIMIZE
rvclkhdr lsu_freeze_c1dc2_cgc ( .en(lsu_freeze_c1_dc2_clken), .l1clk(lsu_freeze_c1_dc2_clk), .* ); assign lsu_freeze_c1_dc2_clk = 1'b0;
rvclkhdr lsu_freeze_c1dc3_cgc ( .en(lsu_freeze_c1_dc3_clken), .l1clk(lsu_freeze_c1_dc3_clk), .* ); assign lsu_freeze_c1_dc3_clk = 1'b0;
assign lsu_freeze_c2_dc1_clk = 1'b0;
assign lsu_freeze_c2_dc2_clk = 1'b0;
assign lsu_freeze_c2_dc3_clk = 1'b0;
assign lsu_freeze_c2_dc4_clk = 1'b0;
rvclkhdr lsu_freeze_c2dc1_cgc ( .en(lsu_freeze_c2_dc1_clken), .l1clk(lsu_freeze_c2_dc1_clk), .* ); assign lsu_busm_clk = 1'b0;
rvclkhdr lsu_freeze_c2dc2_cgc ( .en(lsu_freeze_c2_dc2_clken), .l1clk(lsu_freeze_c2_dc2_clk), .* ); assign lsu_dccm_c1_dc3_clk = 1'b0;
rvclkhdr lsu_freeze_c2dc3_cgc ( .en(lsu_freeze_c2_dc3_clken), .l1clk(lsu_freeze_c2_dc3_clk), .* );
rvclkhdr lsu_freeze_c2dc4_cgc ( .en(lsu_freeze_c2_dc4_clken), .l1clk(lsu_freeze_c2_dc4_clk), .* ); `else
rvclkhdr lsu_freeze_c1dc2_cgc ( .en(lsu_freeze_c1_dc2_clken), .l1clk(lsu_freeze_c1_dc2_clk), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr lsu_freeze_c1dc3_cgc ( .en(lsu_freeze_c1_dc3_clken), .l1clk(lsu_freeze_c1_dc3_clk), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr lsu_freeze_c2dc1_cgc ( .en(lsu_freeze_c2_dc1_clken), .l1clk(lsu_freeze_c2_dc1_clk), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr lsu_freeze_c2dc2_cgc ( .en(lsu_freeze_c2_dc2_clken), .l1clk(lsu_freeze_c2_dc2_clk), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr lsu_freeze_c2dc3_cgc ( .en(lsu_freeze_c2_dc3_clken), .l1clk(lsu_freeze_c2_dc3_clk), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr lsu_freeze_c2dc4_cgc ( .en(lsu_freeze_c2_dc4_clken), .l1clk(lsu_freeze_c2_dc4_clk), .* ); // ifndef FPGA_OPTIMIZE
rvclkhdr lsu_busm_cgc (.en(lsu_bus_clk_en), .l1clk(lsu_busm_clk), .*); // ifndef FPGA_OPTIMIZE
rvclkhdr lsu_dccm_c1dc3_cgc (.en(lsu_dccm_c1_dc3_clken), .l1clk(lsu_dccm_c1_dc3_clk), .*); // ifndef FPGA_OPTIMIZE
`endif
rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* ); rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* );
rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* ); rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* );
rvoclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* ); rvoclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );
rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken), .l1clk(lsu_bus_buf_c1_clk), .* ); rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken), .l1clk(lsu_bus_buf_c1_clk), .* );
rvclkhdr lsu_busm_cgc (.en(lsu_bus_clk_en), .l1clk(lsu_busm_clk), .*);
rvclkhdr lsu_dccm_c1dc3_cgc (.en(lsu_dccm_c1_dc3_clken), .l1clk(lsu_dccm_c1_dc3_clk), .*);
// rvclkhdr lsu_pic_c1dc3_cgc (.en(lsu_pic_c1_dc3_clken), .l1clk(lsu_pic_c1_dc3_clk), .*);
rvclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*); rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*);
endmodule endmodule

16
design/lsu/lsu_dccm_ctl.sv
View File

@ -31,7 +31,10 @@ module lsu_dccm_ctl
( (
input logic lsu_freeze_c2_dc2_clk, // clocks input logic lsu_freeze_c2_dc2_clk, // clocks
input logic lsu_freeze_c2_dc3_clk, input logic lsu_freeze_c2_dc3_clk,
input logic lsu_freeze_c2_dc2_clken, // clocks
input logic lsu_freeze_c2_dc3_clken,
input logic lsu_dccm_c1_dc3_clk, input logic lsu_dccm_c1_dc3_clk,
input logic lsu_dccm_c1_dc3_clken,
input logic lsu_pic_c1_dc3_clken, input logic lsu_pic_c1_dc3_clken,
input logic rst_l, input logic rst_l,
@ -178,14 +181,15 @@ module lsu_dccm_ctl
assign picm_rd_data_dc3[63:0] = {picm_rd_data_lo_dc3[31:0], picm_rd_data_lo_dc3[31:0]} ; assign picm_rd_data_dc3[63:0] = {picm_rd_data_lo_dc3[31:0], picm_rd_data_lo_dc3[31:0]} ;
rvdffe #(32) picm_data_ff (.*, .din(picm_rd_data[31:0]), .dout(picm_rd_data_lo_dc3[31:0]), .en(lsu_pic_c1_dc3_clken)); rvdffe #(32) picm_data_ff (.*, .din(picm_rd_data[31:0]), .dout(picm_rd_data_lo_dc3[31:0]), .en(lsu_pic_c1_dc3_clken));
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
rvdff #(1) dccm_rden_dc2ff (.*, .din(lsu_dccm_rden_dc1), .dout(lsu_dccm_rden_dc2), .clk(lsu_freeze_c2_dc2_clk));
rvdff #(1) dccm_rden_dc3ff (.*, .din(lsu_dccm_rden_dc2), .dout(lsu_dccm_rden_dc3), .clk(lsu_freeze_c2_dc3_clk));
rvdff #(DCCM_DATA_WIDTH) dccm_data_hi_ff (.*, .din(dccm_data_hi_dc2[DCCM_DATA_WIDTH-1:0]), .dout(dccm_data_hi_dc3[DCCM_DATA_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk)); rvdff_fpga #(1) dccm_rden_dc2ff (.*, .din(lsu_dccm_rden_dc1), .dout(lsu_dccm_rden_dc2), .clk(lsu_freeze_c2_dc2_clk), .clken(lsu_freeze_c2_dc2_clken), .rawclk(clk));
rvdff #(DCCM_DATA_WIDTH) dccm_data_lo_ff (.*, .din(dccm_data_lo_dc2[DCCM_DATA_WIDTH-1:0]), .dout(dccm_data_lo_dc3[DCCM_DATA_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk)); rvdff_fpga #(1) dccm_rden_dc3ff (.*, .din(lsu_dccm_rden_dc2), .dout(lsu_dccm_rden_dc3), .clk(lsu_freeze_c2_dc3_clk), .clken(lsu_freeze_c2_dc3_clken), .rawclk(clk));
rvdff_fpga #(DCCM_DATA_WIDTH) dccm_data_hi_ff (.*, .din(dccm_data_hi_dc2[DCCM_DATA_WIDTH-1:0]), .dout(dccm_data_hi_dc3[DCCM_DATA_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk), .clken(lsu_dccm_c1_dc3_clken), .rawclk(clk));
rvdff_fpga #(DCCM_DATA_WIDTH) dccm_data_lo_ff (.*, .din(dccm_data_lo_dc2[DCCM_DATA_WIDTH-1:0]), .dout(dccm_data_lo_dc3[DCCM_DATA_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk), .clken(lsu_dccm_c1_dc3_clken), .rawclk(clk));
rvdff_fpga #(DCCM_ECC_WIDTH) dccm_data_ecc_hi_ff (.*, .din(dccm_data_ecc_hi_dc2[DCCM_ECC_WIDTH-1:0]), .dout(dccm_data_ecc_hi_dc3[DCCM_ECC_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk), .clken(lsu_dccm_c1_dc3_clken), .rawclk(clk));
rvdff_fpga #(DCCM_ECC_WIDTH) dccm_data_ecc_lo_ff (.*, .din(dccm_data_ecc_lo_dc2[DCCM_ECC_WIDTH-1:0]), .dout(dccm_data_ecc_lo_dc3[DCCM_ECC_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk), .clken(lsu_dccm_c1_dc3_clken), .rawclk(clk));
rvdff #(DCCM_ECC_WIDTH) dccm_data_ecc_hi_ff (.*, .din(dccm_data_ecc_hi_dc2[DCCM_ECC_WIDTH-1:0]), .dout(dccm_data_ecc_hi_dc3[DCCM_ECC_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk));
rvdff #(DCCM_ECC_WIDTH) dccm_data_ecc_lo_ff (.*, .din(dccm_data_ecc_lo_dc2[DCCM_ECC_WIDTH-1:0]), .dout(dccm_data_ecc_lo_dc3[DCCM_ECC_WIDTH-1:0]), .clk(lsu_dccm_c1_dc3_clk));
end else begin: Gen_dccm_disable end else begin: Gen_dccm_disable
assign lsu_dccm_rden_dc2 = '0; assign lsu_dccm_rden_dc2 = '0;
assign lsu_dccm_rden_dc3 = '0; assign lsu_dccm_rden_dc3 = '0;

20
design/lsu/lsu_dccm_mem.sv
View File

@ -30,6 +30,7 @@ module lsu_dccm_mem
import swerv_types::*; import swerv_types::*;
( (
input logic clk, // clock input logic clk, // clock
input logic free_clk, // clock
input logic rst_l, input logic rst_l,
input logic lsu_freeze_dc3, // freeze input logic lsu_freeze_dc3, // freeze
input logic clk_override, // clock override input logic clk_override, // clock override
@ -71,11 +72,24 @@ module lsu_dccm_mem
logic [DCCM_NUM_BANKS-1:0] dccm_clk; logic [DCCM_NUM_BANKS-1:0] dccm_clk;
logic [DCCM_NUM_BANKS-1:0] dccm_clken; logic [DCCM_NUM_BANKS-1:0] dccm_clken;
logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo_q, dccm_rd_data_hi_q;
logic lsu_freeze_dc3_q;
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]); assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
`ifdef RV_FPGA_OPTIMIZE
// Align the read data
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = lsu_freeze_dc3_q ? dccm_rd_data_lo_q[DCCM_FDATA_WIDTH-1:0] : dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = lsu_freeze_dc3_q ? dccm_rd_data_hi_q[DCCM_FDATA_WIDTH-1:0] : dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
rvdff #(1) lsu_freeze_dc3ff(.din(lsu_freeze_dc3), .dout(lsu_freeze_dc3_q), .clk(free_clk), .*);
rvdffe #(DCCM_FDATA_WIDTH) dccm_rd_data_loff(.din(dccm_rd_data_lo), .dout(dccm_rd_data_lo_q), .en(~lsu_freeze_dc3_q), .*);
rvdffe #(DCCM_FDATA_WIDTH) dccm_rd_data_hiff(.din(dccm_rd_data_hi), .dout(dccm_rd_data_hi_q), .en(~lsu_freeze_dc3_q), .*);
`else
// Align the read data // Align the read data
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
`endif
// Generate even/odd address // Generate even/odd address
// assign rd_addr_even[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = dccm_rd_addr_lo[2] ? dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] : // assign rd_addr_even[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = dccm_rd_addr_lo[2] ? dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
@ -103,7 +117,7 @@ module lsu_dccm_mem
// clock gating section // clock gating section
assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) & ~lsu_freeze_dc3; assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) & ~lsu_freeze_dc3;
rvclkhdr lsu_dccm_cgc (.en(dccm_clken[i]), .l1clk(dccm_clk[i]), .*); rvoclkhdr lsu_dccm_cgc (.en(dccm_clken[i]), .l1clk(dccm_clk[i]), .*);
// end clock gating section // end clock gating section
`RV_DCCM_DATA_CELL dccm_bank ( `RV_DCCM_DATA_CELL dccm_bank (
@ -119,8 +133,8 @@ module lsu_dccm_mem
end : mem_bank end : mem_bank
// Flops // Flops
rvdffs #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(~lsu_freeze_dc3)); rvdffs #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(~lsu_freeze_dc3), .clk(free_clk));
rvdffs #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(~lsu_freeze_dc3)); rvdffs #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(~lsu_freeze_dc3), .clk(free_clk));
endmodule // lsu_dccm_mem endmodule // lsu_dccm_mem

29
design/lsu/lsu_lsc_ctl.sv
View File

@ -45,6 +45,9 @@ module lsu_lsc_ctl
input logic lsu_freeze_c2_dc1_clk, input logic lsu_freeze_c2_dc1_clk,
input logic lsu_freeze_c2_dc2_clk, input logic lsu_freeze_c2_dc2_clk,
input logic lsu_freeze_c2_dc3_clk, input logic lsu_freeze_c2_dc3_clk,
input logic lsu_freeze_c2_dc1_clken,
input logic lsu_freeze_c2_dc2_clken,
input logic lsu_freeze_c2_dc3_clken,
input logic lsu_store_c1_dc1_clken, input logic lsu_store_c1_dc1_clken,
input logic lsu_store_c1_dc2_clken, input logic lsu_store_c1_dc2_clken,
@ -248,9 +251,6 @@ module lsu_lsc_ctl
end end
// C2 clock for valid and C1 for other bits of packet // C2 clock for valid and C1 for other bits of packet
rvdff #(1) lsu_pkt_vlddc1ff (.*, .din(lsu_pkt_dc1_in.valid), .dout(lsu_pkt_dc1.valid), .clk(lsu_freeze_c2_dc1_clk));
rvdff #(1) lsu_pkt_vlddc2ff (.*, .din(lsu_pkt_dc2_in.valid), .dout(lsu_pkt_dc2.valid), .clk(lsu_freeze_c2_dc2_clk));
rvdff #(1) lsu_pkt_vlddc3ff (.*, .din(lsu_pkt_dc3_in.valid), .dout(lsu_pkt_dc3.valid), .clk(lsu_freeze_c2_dc3_clk));
rvdff #(1) lsu_pkt_vlddc4ff (.*, .din(lsu_pkt_dc4_in.valid), .dout(lsu_pkt_dc4.valid), .clk(lsu_c2_dc4_clk)); rvdff #(1) lsu_pkt_vlddc4ff (.*, .din(lsu_pkt_dc4_in.valid), .dout(lsu_pkt_dc4.valid), .clk(lsu_c2_dc4_clk));
rvdff #(1) lsu_pkt_vlddc5ff (.*, .din(lsu_pkt_dc5_in.valid), .dout(lsu_pkt_dc5.valid), .clk(lsu_c2_dc5_clk)); rvdff #(1) lsu_pkt_vlddc5ff (.*, .din(lsu_pkt_dc5_in.valid), .dout(lsu_pkt_dc5.valid), .clk(lsu_c2_dc5_clk));
@ -321,19 +321,22 @@ module lsu_lsc_ctl
rvdff #(32) end_addr_dc4ff (.*, .din(end_addr_dc3[31:0]), .dout(end_addr_dc4[31:0]), .clk(lsu_c1_dc4_clk)); rvdff #(32) end_addr_dc4ff (.*, .din(end_addr_dc3[31:0]), .dout(end_addr_dc4[31:0]), .clk(lsu_c1_dc4_clk));
rvdff #(32) end_addr_dc5ff (.*, .din(end_addr_dc4[31:0]), .dout(end_addr_dc5[31:0]), .clk(lsu_c1_dc5_clk)); rvdff #(32) end_addr_dc5ff (.*, .din(end_addr_dc4[31:0]), .dout(end_addr_dc5[31:0]), .clk(lsu_c1_dc5_clk));
rvdff #(1) addr_in_dccm_dc2ff(.din(addr_in_dccm_dc1), .dout(addr_in_dccm_dc2), .clk(lsu_freeze_c1_dc2_clk), .*); rvdff_fpga #(1) addr_in_dccm_dc2ff (.din(addr_in_dccm_dc1), .dout(addr_in_dccm_dc2), .clk(lsu_freeze_c1_dc2_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc2_clken), .*);
rvdff #(1) addr_in_dccm_dc3ff(.din(addr_in_dccm_dc2), .dout(addr_in_dccm_dc3), .clk(lsu_freeze_c1_dc3_clk), .*); rvdff_fpga #(1) addr_in_dccm_dc3ff (.din(addr_in_dccm_dc2), .dout(addr_in_dccm_dc3), .clk(lsu_freeze_c1_dc3_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc3_clken), .*);
rvdff #(1) addr_in_pic_dc2ff(.din(addr_in_pic_dc1), .dout(addr_in_pic_dc2), .clk(lsu_freeze_c1_dc2_clk), .*); rvdff_fpga #(1) addr_in_pic_dc2ff (.din(addr_in_pic_dc1), .dout(addr_in_pic_dc2), .clk(lsu_freeze_c1_dc2_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc2_clken), .*);
rvdff #(1) addr_in_pic_dc3ff(.din(addr_in_pic_dc2), .dout(addr_in_pic_dc3), .clk(lsu_freeze_c1_dc3_clk), .*); rvdff_fpga #(1) addr_in_pic_dc3ff (.din(addr_in_pic_dc2), .dout(addr_in_pic_dc3), .clk(lsu_freeze_c1_dc3_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc3_clken), .*);
rvdff_fpga #(1) access_fault_dc2ff (.din(access_fault_dc1), .dout(access_fault_dc2), .clk(lsu_freeze_c1_dc2_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc2_clken), .*);
rvdff_fpga #(1) access_fault_dc3ff (.din(access_fault_dc2), .dout(access_fault_dc3), .clk(lsu_freeze_c1_dc3_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc3_clken), .*);
rvdff_fpga #(1) addr_external_dc2ff (.din(addr_external_dc1), .dout(addr_external_dc2), .clk(lsu_freeze_c1_dc2_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc2_clken), .*);
rvdff_fpga #(1) addr_external_dc3ff (.din(addr_external_dc2), .dout(addr_external_dc3), .clk(lsu_freeze_c1_dc3_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc3_clken), .*);
rvdff_fpga #(1) misaligned_fault_dc2ff (.din(misaligned_fault_dc1), .dout(misaligned_fault_dc2), .clk(lsu_freeze_c1_dc2_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc2_clken), .*);
rvdff_fpga #(1) misaligned_fault_dc3ff (.din(misaligned_fault_dc2), .dout(misaligned_fault_dc3), .clk(lsu_freeze_c1_dc3_clk), .rawclk(clk), .clken(lsu_freeze_c1_dc3_clken), .*);
rvdff_fpga #(1) lsu_pkt_vlddc1ff (.din(lsu_pkt_dc1_in.valid), .dout(lsu_pkt_dc1.valid), .clk(lsu_freeze_c2_dc1_clk), .rawclk(clk), .clken(lsu_freeze_c2_dc1_clken), .*);
rvdff_fpga #(1) lsu_pkt_vlddc2ff (.din(lsu_pkt_dc2_in.valid), .dout(lsu_pkt_dc2.valid), .clk(lsu_freeze_c2_dc2_clk), .rawclk(clk), .clken(lsu_freeze_c2_dc2_clken), .*);
rvdff_fpga #(1) lsu_pkt_vlddc3ff (.din(lsu_pkt_dc3_in.valid), .dout(lsu_pkt_dc3.valid), .clk(lsu_freeze_c2_dc3_clk), .rawclk(clk), .clken(lsu_freeze_c2_dc3_clken), .*);
rvdff #(1) addr_external_dc2ff(.din(addr_external_dc1), .dout(addr_external_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
rvdff #(1) addr_external_dc3ff(.din(addr_external_dc2), .dout(addr_external_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
rvdff #(1) addr_external_dc4ff(.din(addr_external_dc3), .dout(addr_external_dc4), .clk(lsu_c1_dc4_clk), .*); rvdff #(1) addr_external_dc4ff(.din(addr_external_dc3), .dout(addr_external_dc4), .clk(lsu_c1_dc4_clk), .*);
rvdff #(1) addr_external_dc5ff(.din(addr_external_dc4), .dout(addr_external_dc5), .clk(lsu_c1_dc5_clk), .*); rvdff #(1) addr_external_dc5ff(.din(addr_external_dc4), .dout(addr_external_dc5), .clk(lsu_c1_dc5_clk), .*);
rvdff #(1) access_fault_dc2ff(.din(access_fault_dc1), .dout(access_fault_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
rvdff #(1) access_fault_dc3ff(.din(access_fault_dc2), .dout(access_fault_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
rvdff #(1) misaligned_fault_dc2ff(.din(misaligned_fault_dc1), .dout(misaligned_fault_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
rvdff #(1) misaligned_fault_dc3ff(.din(misaligned_fault_dc2), .dout(misaligned_fault_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
endmodule endmodule

12
design/lsu/lsu_stbuf.sv
View File

@ -38,6 +38,9 @@ module lsu_stbuf
input logic lsu_freeze_c1_dc2_clk, // freeze clock input logic lsu_freeze_c1_dc2_clk, // freeze clock
input logic lsu_freeze_c1_dc3_clk, // freeze clock input logic lsu_freeze_c1_dc3_clk, // freeze clock
input logic lsu_freeze_c2_dc2_clken,
input logic lsu_freeze_c2_dc3_clken,
input logic lsu_freeze_c1_dc2_clken,
input logic lsu_freeze_c1_dc3_clken, input logic lsu_freeze_c1_dc3_clken,
input logic lsu_c1_dc4_clk, // lsu pipe clock input logic lsu_c1_dc4_clk, // lsu pipe clock
@ -232,8 +235,11 @@ module lsu_stbuf
rvdff #(.WIDTH(DEPTH_LOG2)) WrPtr_dc4ff (.din(WrPtr_dc3[DEPTH_LOG2-1:0]), .dout(WrPtr_dc4[DEPTH_LOG2-1:0]), .clk(lsu_c1_dc4_clk), .*); rvdff #(.WIDTH(DEPTH_LOG2)) WrPtr_dc4ff (.din(WrPtr_dc3[DEPTH_LOG2-1:0]), .dout(WrPtr_dc4[DEPTH_LOG2-1:0]), .clk(lsu_c1_dc4_clk), .*);
rvdff #(.WIDTH(DEPTH_LOG2)) WrPtr_dc5ff (.din(WrPtr_dc4[DEPTH_LOG2-1:0]), .dout(WrPtr_dc5[DEPTH_LOG2-1:0]), .clk(lsu_c1_dc5_clk), .*); rvdff #(.WIDTH(DEPTH_LOG2)) WrPtr_dc5ff (.din(WrPtr_dc4[DEPTH_LOG2-1:0]), .dout(WrPtr_dc5[DEPTH_LOG2-1:0]), .clk(lsu_c1_dc5_clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc2ff (.din(ldst_dual_dc1), .dout(ldst_dual_dc2), .clk(lsu_freeze_c1_dc2_clk), .*); rvdff_fpga #(.WIDTH(1)) ldst_dual_dc2ff (.din(ldst_dual_dc1), .dout(ldst_dual_dc2), .clk(lsu_freeze_c1_dc2_clk), .clken(lsu_freeze_c1_dc2_clken), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc3ff (.din(ldst_dual_dc2), .dout(ldst_dual_dc3), .clk(lsu_freeze_c1_dc3_clk), .*); rvdff_fpga #(.WIDTH(1)) ldst_dual_dc3ff (.din(ldst_dual_dc2), .dout(ldst_dual_dc3), .clk(lsu_freeze_c1_dc3_clk), .clken(lsu_freeze_c1_dc3_clken), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(BYTE_WIDTH)) stbuf_fwdbyteen_hi_dc3ff (.din(stbuf_fwdbyteen_hi_fn_dc2[BYTE_WIDTH-1:0]), .dout(stbuf_fwdbyteen_hi_dc3[BYTE_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .clken(lsu_freeze_c1_dc3_clken), .rawclk(clk), .*);
rvdff_fpga #(.WIDTH(BYTE_WIDTH)) stbuf_fwdbyteen_lo_dc3ff (.din(stbuf_fwdbyteen_lo_fn_dc2[BYTE_WIDTH-1:0]), .dout(stbuf_fwdbyteen_lo_dc3[BYTE_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .clken(lsu_freeze_c1_dc3_clken), .rawclk(clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc4ff (.din(ldst_dual_dc3), .dout(ldst_dual_dc4), .clk(lsu_c1_dc4_clk), .*); rvdff #(.WIDTH(1)) ldst_dual_dc4ff (.din(ldst_dual_dc3), .dout(ldst_dual_dc4), .clk(lsu_c1_dc4_clk), .*);
rvdff #(.WIDTH(1)) ldst_dual_dc5ff (.din(ldst_dual_dc4), .dout(ldst_dual_dc5), .clk(lsu_c1_dc5_clk), .*); rvdff #(.WIDTH(1)) ldst_dual_dc5ff (.din(ldst_dual_dc4), .dout(ldst_dual_dc5), .clk(lsu_c1_dc5_clk), .*);
@ -387,8 +393,6 @@ module lsu_stbuf
rvdffs #(.WIDTH(DEPTH_LOG2)) WrPtrff (.din(NxtWrPtr[DEPTH_LOG2-1:0]), .dout(WrPtr[DEPTH_LOG2-1:0]), .en(WrPtrEn), .clk(lsu_stbuf_c1_clk), .*); rvdffs #(.WIDTH(DEPTH_LOG2)) WrPtrff (.din(NxtWrPtr[DEPTH_LOG2-1:0]), .dout(WrPtr[DEPTH_LOG2-1:0]), .en(WrPtrEn), .clk(lsu_stbuf_c1_clk), .*);
rvdffs #(.WIDTH(DEPTH_LOG2)) RdPtrff (.din(NxtRdPtr[DEPTH_LOG2-1:0]), .dout(RdPtr[DEPTH_LOG2-1:0]), .en(RdPtrEn), .clk(lsu_stbuf_c1_clk), .*); rvdffs #(.WIDTH(DEPTH_LOG2)) RdPtrff (.din(NxtRdPtr[DEPTH_LOG2-1:0]), .dout(RdPtr[DEPTH_LOG2-1:0]), .en(RdPtrEn), .clk(lsu_stbuf_c1_clk), .*);
rvdff #(.WIDTH(BYTE_WIDTH)) stbuf_fwdbyteen_hi_dc3ff (.din(stbuf_fwdbyteen_hi_fn_dc2[BYTE_WIDTH-1:0]), .dout(stbuf_fwdbyteen_hi_dc3[BYTE_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .*);
rvdff #(.WIDTH(BYTE_WIDTH)) stbuf_fwdbyteen_lo_dc3ff (.din(stbuf_fwdbyteen_lo_fn_dc2[BYTE_WIDTH-1:0]), .dout(stbuf_fwdbyteen_lo_dc3[BYTE_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .*);
rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_hi_dc3ff (.din(stbuf_fwddata_hi_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_hi_dc3[DATA_WIDTH-1:0]), .en(lsu_freeze_c1_dc3_clken), .*); rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_hi_dc3ff (.din(stbuf_fwddata_hi_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_hi_dc3[DATA_WIDTH-1:0]), .en(lsu_freeze_c1_dc3_clken), .*);
rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_lo_dc3ff (.din(stbuf_fwddata_lo_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_lo_dc3[DATA_WIDTH-1:0]), .en(lsu_freeze_c1_dc3_clken), .*); rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_lo_dc3ff (.din(stbuf_fwddata_lo_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_lo_dc3[DATA_WIDTH-1:0]), .en(lsu_freeze_c1_dc3_clken), .*);

5
design/mem.sv
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@ -50,7 +50,7 @@ module mem
`endif `endif
// Icache and Itag Ports // Icache and Itag Ports
`ifdef RV_ICACHE_ENABLE //temp `ifdef RV_ICACHE_ENABLE //temp
input logic [31:3] ic_rw_addr, input logic [31:2] ic_rw_addr,
input logic [3:0] ic_tag_valid, input logic [3:0] ic_tag_valid,
input logic [3:0] ic_wr_en, input logic [3:0] ic_wr_en,
input logic ic_rd_en, input logic ic_rd_en,
@ -98,6 +98,9 @@ module mem
localparam DCCM_ENABLE = 1'b0; localparam DCCM_ENABLE = 1'b0;
`endif `endif
logic free_clk;
rvoclkhdr free_cg ( .en(1'b1), .l1clk(free_clk), .* );
// DCCM Instantiation // DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem dccm ( lsu_dccm_mem dccm (

6
design/pic_ctrl.sv
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@ -201,7 +201,7 @@ for (i=0; i<TOTAL_INT ; i++) begin : SETREG
// if (GW_CONFIG[i]) begin // if (GW_CONFIG[i]) begin
rvdffs #(2) gw_config_ff (.*, .en( gw_config_reg_we[i]), .din (picm_wr_data_ff[1:0]), .dout(gw_config_reg[i]), .clk(gw_config_c1_clk)); rvdffs #(2) gw_config_ff (.*, .en( gw_config_reg_we[i]), .din (picm_wr_data_ff[1:0]), .dout(gw_config_reg[i]), .clk(gw_config_c1_clk));
configurable_gw config_gw_inst(.*, .clk(free_clk), configurable_gw config_gw_inst(.*, .gw_clk(free_clk),
.extintsrc_req_sync(extintsrc_req_sync[i]) , .extintsrc_req_sync(extintsrc_req_sync[i]) ,
.meigwctrl_polarity(gw_config_reg[i][0]) , .meigwctrl_polarity(gw_config_reg[i][0]) ,
.meigwctrl_type(gw_config_reg[i][1]) , .meigwctrl_type(gw_config_reg[i][1]) ,
@ -478,7 +478,7 @@ endmodule // cmp_and_mux
module configurable_gw ( module configurable_gw (
input logic clk, input logic gw_clk,
input logic rst_l, input logic rst_l,
input logic extintsrc_req_sync , input logic extintsrc_req_sync ,
@ -493,7 +493,7 @@ module configurable_gw (
logic gw_int_pending_in , gw_int_pending ; logic gw_int_pending_in , gw_int_pending ;
assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr) ; assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr) ;
rvdff #(1) int_pend_ff (.*, .clk(clk), .din (gw_int_pending_in), .dout(gw_int_pending)); rvdff #(1) int_pend_ff (.*, .clk(gw_clk), .din (gw_int_pending_in), .dout(gw_int_pending));
assign extintsrc_req_config = meigwctrl_type ? ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending) : (extintsrc_req_sync ^ meigwctrl_polarity) ; assign extintsrc_req_config = meigwctrl_type ? ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending) : (extintsrc_req_sync ^ meigwctrl_polarity) ;

2
design/swerv.sv
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@ -89,7 +89,7 @@ module swerv
`endif `endif
// ICache , ITAG ports // ICache , ITAG ports
output logic [31:3] ic_rw_addr, output logic [31:2] ic_rw_addr,
output logic [3:0] ic_tag_valid, output logic [3:0] ic_tag_valid,
output logic [3:0] ic_wr_en, output logic [3:0] ic_wr_en,
output logic ic_rd_en, output logic ic_rd_en,

2
design/swerv_wrapper.sv
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@ -346,7 +346,7 @@ module swerv_wrapper
// PIC ports // PIC ports
// Icache & Itag ports // Icache & Itag ports
logic [31:3] ic_rw_addr; logic [31:2] ic_rw_addr;
logic [3:0] ic_wr_en ; // Which way to write logic [3:0] ic_wr_en ; // Which way to write
logic ic_rd_en ; logic ic_rd_en ;

4
docs/README.md
View File

@ -1,8 +1,8 @@
# RISC-V SweRV EH1 V1.6 core from Western Digital # RISC-V SweRV EH1 1.5 core from Western Digital
## Documentation ## Documentation
### Contents ### Contents
Name | Description Name | Description
---------------------- | ------------------------------ ---------------------- | ------------------------------
RISC-V_SweRV_EH1_PRM.pdf | Programmer's Reference Manual V1.6 for SweRV EH1 core RISC-V_SweRV_EH1_PRM.pdf | Programmer's Reference Manual V1.5 for SweRV EH1 core

11
release-notes.md
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@ -1,3 +1,14 @@
# SweRV RISC-V Core<sup>TM</sup> 1.7 from Western Digital
## Release Notes
* RV_FPGA_OPTIMIZE is now default build option.
* Use -fpga_optimize=0 to build for lower power (ASIC) flows.
* Fixed a couple of cases of clock enable qualification for power reduction
* Fixes for 4 debug compliance issues reported by Codasip
* Fixed some remaining clock gating issues for RV_FPGA_OPTIMIZE to improve fpga speed
# SweRV RISC-V Core<sup>TM</sup> 1.6 from Western Digital # SweRV RISC-V Core<sup>TM</sup> 1.6 from Western Digital
## Release Notes ## Release Notes