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Change clock header instance name in beh_lib.sv

This commit is contained in:
Joseph Rahmeh 2019-09-04 14:39:10 -07:00
parent 35bc589b09
commit 811e9c3d24
5 changed files with 6 additions and 6 deletions
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2
configs/snapshots/default/common_defines.vh
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@ -1,5 +1,5 @@
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
// This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
//
// cmd: swerv -snapshot=default -ahb_lite
//

2
configs/snapshots/default/defines.h
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@ -1,5 +1,5 @@
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
// This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
//
// cmd: swerv -snapshot=default -ahb_lite
//

2
configs/snapshots/default/pd_defines.vh
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@ -1,5 +1,5 @@
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
// This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
// This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
//
// cmd: swerv -snapshot=default -ahb_lite
//

2
configs/snapshots/default/perl_configs.pl
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@ -1,5 +1,5 @@
# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
# This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
# This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
#
# cmd: swerv -snapshot=default -ahb_lite
#

4
design/lib/beh_lib.sv
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@ -108,7 +108,7 @@ module rvclkhdr
logic TE;
assign TE = scan_mode;
`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
`TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
endmodule
@ -126,7 +126,7 @@ module rvoclkhdr
`ifdef RV_FPGA_OPTIMIZE
assign l1clk = clk;
`else
`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
`TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
`endif
endmodule