Change clock header instance name in beh_lib.sv
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35bc589b09
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811e9c3d24
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@ -1,5 +1,5 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
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// This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
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//
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//
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// cmd: swerv -snapshot=default -ahb_lite
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// cmd: swerv -snapshot=default -ahb_lite
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//
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//
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@ -1,5 +1,5 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
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// This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
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//
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//
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// cmd: swerv -snapshot=default -ahb_lite
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// cmd: swerv -snapshot=default -ahb_lite
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//
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//
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@ -1,5 +1,5 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
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// This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
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//
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//
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// cmd: swerv -snapshot=default -ahb_lite
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// cmd: swerv -snapshot=default -ahb_lite
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//
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//
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@ -1,5 +1,5 @@
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# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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# This is an automatically generated file by joseph.rahmeh on Tue Aug 13 12:51:42 PDT 2019
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# This is an automatically generated file by joseph.rahmeh on Wed Sep 4 13:31:40 PDT 2019
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#
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#
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# cmd: swerv -snapshot=default -ahb_lite
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# cmd: swerv -snapshot=default -ahb_lite
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#
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#
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@ -108,7 +108,7 @@ module rvclkhdr
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logic TE;
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logic TE;
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assign TE = scan_mode;
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assign TE = scan_mode;
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`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
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`TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
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endmodule
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endmodule
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@ -126,7 +126,7 @@ module rvoclkhdr
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`ifdef RV_FPGA_OPTIMIZE
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`ifdef RV_FPGA_OPTIMIZE
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assign l1clk = clk;
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assign l1clk = clk;
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`else
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`else
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`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
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`TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
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`endif
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`endif
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endmodule
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endmodule
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