Add pyfpga to gen xc7z010.
This commit is contained in:
Colin
parent
148c4c2d4b
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8171eabec1
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build
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//`include "global_define.v"
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module TOP(
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inout wire [14:0] DDR_addr,
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inout wire [2:0] DDR_ba,
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inout wire DDR_cas_n,
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inout wire DDR_ck_n,
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inout wire DDR_ck_p,
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inout wire DDR_cke,
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inout wire DDR_cs_n,
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inout wire [3:0] DDR_dm,
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inout wire [31:0] DDR_dq,
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inout wire [3:0] DDR_dqs_n,
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inout wire [3:0] DDR_dqs_p,
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inout wire DDR_odt,
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inout wire DDR_ras_n,
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inout wire DDR_reset_n,
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inout wire DDR_we_n,
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inout wire FIXED_IO_ddr_vrn,
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inout wire FIXED_IO_ddr_vrp,
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inout wire [53:0] FIXED_IO_mio,
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inout wire FIXED_IO_ps_clk,
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inout wire FIXED_IO_ps_porb,
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inout wire FIXED_IO_ps_srstb,
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//misc
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//input wire key,
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output wire led1,
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output wire led2,
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output wire led3,
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input wire uart_rx,
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output wire uart_tx
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);
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// assign led1 = ~vout_lvds_mmcm_locked;
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// assign led2 = ~led_b;
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wire led_b;
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wire clk_axi;
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design_1 u_bd(
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.DDR_addr (DDR_addr ),
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.DDR_ba (DDR_ba ),
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.DDR_cas_n (DDR_cas_n ),
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.DDR_ck_n (DDR_ck_n ),
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.DDR_ck_p (DDR_ck_p ),
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.DDR_cke (DDR_cke ),
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.DDR_cs_n (DDR_cs_n ),
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.DDR_dm (DDR_dm ),
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.DDR_dq (DDR_dq ),
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.DDR_dqs_n (DDR_dqs_n ),
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.DDR_dqs_p (DDR_dqs_p ),
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.DDR_odt (DDR_odt ),
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.DDR_ras_n (DDR_ras_n ),
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.DDR_reset_n (DDR_reset_n ),
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.DDR_we_n (DDR_we_n ),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ),
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.FIXED_IO_mio (FIXED_IO_mio ),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb ),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb ),
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.UART_rxd (uart_rx ),
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.UART_txd (uart_tx ),
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.clk_axi (clk_axi ),
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.rstn_axi ( )
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);
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//--------------------------------led----------------------------------
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led led_breath(
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.clk (clk_axi ),
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.led (led_b )
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);
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assign led1 = led_b;
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assign led2 = led_b;
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assign led3 = led_b;
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endmodule
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File diff suppressed because it is too large
Load Diff
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<?xml version="1.0" encoding="utf-8"?>
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<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
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<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
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<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
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<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
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<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
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<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
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<key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
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<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
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<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
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<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
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<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
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<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
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<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
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<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
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<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
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<key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
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<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
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<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
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<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
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<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
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<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
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<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
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<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
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<node id="n0">
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<data key="VM">design_1</data>
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<data key="VT">BC</data>
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</node>
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<node id="n1">
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<data key="VH">2</data>
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<data key="VM">design_1</data>
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<data key="VT">VR</data>
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</node>
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<node id="n2">
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<data key="TU">active</data>
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<data key="VH">2</data>
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<data key="VT">PM</data>
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</node>
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<edge id="e0" source="n0" target="n1"/>
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<edge id="e1" source="n1" target="n2"/>
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</graph>
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</graphml>
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File diff suppressed because it is too large
Load Diff
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{
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"ActiveEmotionalView":"Default View",
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"Default View_ScaleFactor":"1.25",
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"Default View_TopLeft":"-969,-462",
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"ExpandedHierarchyInLayout":"",
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"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
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# -string -flagsOSRD
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preplace port DDR -pg 1 -lvl 2 -x 330 -y 60 -defaultsOSRD
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preplace port FIXED_IO -pg 1 -lvl 2 -x 330 -y 80 -defaultsOSRD
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preplace port UART -pg 1 -lvl 2 -x 330 -y 100 -defaultsOSRD
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preplace port port-id_clk_axi -pg 1 -lvl 2 -x 330 -y 140 -defaultsOSRD
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preplace port port-id_rstn_axi -pg 1 -lvl 2 -x 330 -y 160 -defaultsOSRD
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preplace inst processing_system7_0 -pg 1 -lvl 1 -x 160 -y 110 -defaultsOSRD
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preplace netloc processing_system7_0_FCLK_CLK0 1 1 1 N 140
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preplace netloc processing_system7_0_FCLK_RESET0_N 1 1 1 N 160
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preplace netloc processing_system7_0_DDR 1 1 1 N 60
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preplace netloc processing_system7_0_FIXED_IO 1 1 1 N 80
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preplace netloc processing_system7_0_UART_0 1 1 1 N 100
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levelinfo -pg 1 0 160 330
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pagesize -pg 1 -db -bbox -sgen 0 0 450 220
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"
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}
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0
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{
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"ActiveEmotionalView":"Default View",
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"Default View_ScaleFactor":"1.5",
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"Default View_TopLeft":"-831,-353",
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"ExpandedHierarchyInLayout":"",
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"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
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# -string -flagsOSRD
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preplace port M_AXI -pg 1 -lvl 2 -x 240 -y 70 -defaultsOSRD
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preplace port S_AXI -pg 1 -lvl 0 -x 0 -y 50 -defaultsOSRD
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preplace port port-id_M_ACLK -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
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preplace port port-id_M_ARESETN -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD
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preplace port port-id_S_ACLK -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD
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preplace port port-id_S_ARESETN -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
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preplace inst s01_data_fifo -pg 1 -lvl 1 -x 120 -y 70 -defaultsOSRD
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preplace netloc M_ACLK_1 1 0 1 NJ 70
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preplace netloc M_ARESETN_1 1 0 1 NJ 90
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preplace netloc s01_couplers_to_s01_data_fifo 1 0 1 NJ 50
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preplace netloc s01_data_fifo_to_s01_couplers 1 1 1 N 70
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levelinfo -pg 1 0 120 240
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pagesize -pg 1 -db -bbox -sgen -140 -10 340 150
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"
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}
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module led(
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input wire clk, // 输入时钟
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output reg led // led 输出(高电平有效)
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);
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localparam MAX_DELAY_CNT = 1000000,
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CYCLE_NUMBER = 100; //占空比分为0~100个级别
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reg myclk;
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reg [23:0] delay_cnt;
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reg [7:0] current_cycle;
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reg flag;
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reg [7:0] cycle;
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//--------------------------------------------------------
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// myclk分频
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always@(posedge clk) begin
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if(delay_cnt < MAX_DELAY_CNT)
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delay_cnt <= delay_cnt + 1'b1;
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else begin
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delay_cnt <= 24'd1;
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myclk <= ~myclk;
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end
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end
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//--------------------------------------------------------
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// 0的时候，占空比最小，这个时候直接完全输出高电平，led灯最亮
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// 100的时候，占空比最大，这个时候直接完全输出低电平，led等熄灭
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always@(posedge myclk) begin
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if(flag == 0) begin // 占空比递增
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if(current_cycle < (CYCLE_NUMBER/10))
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current_cycle <= current_cycle + 1'b1;
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else
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flag <= ~flag;
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end
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else begin // 占空比递减
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if(current_cycle > 0)
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current_cycle <= current_cycle - 1'b1;
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else
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flag <= ~flag;
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end
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end
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//--------------------------------------------------------
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// 轮询 0~100个级别的占空比
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always@(posedge clk)
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if(cycle < CYCLE_NUMBER)
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cycle <= cycle + 1'b1;
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else
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cycle <= 1'b1;
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//--------------------------------------------------------
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// cycle小于current_cycle的时候是低电平
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// cycle大于current_cycle并且小于CYCLE_NUMBER的时候是高电平
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always@(posedge clk)
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if((cycle == CYCLE_NUMBER) && (current_cycle != 0))
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led <= 1'b1;
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else if(cycle < current_cycle)
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led <= 1'b1;
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else
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led <= 1'b0;
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endmodule
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#KEY
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set_property PACKAGE_PIN G14 [get_ports key]
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set_property IOSTANDARD LVCMOS33 [get_ports key]
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#LED
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set_property PACKAGE_PIN H15 [get_ports led1]
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set_property IOSTANDARD LVCMOS33 [get_ports led1]
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set_property PACKAGE_PIN G15 [get_ports led2]
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set_property IOSTANDARD LVCMOS33 [get_ports led2]
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set_property PACKAGE_PIN N15 [get_ports led3]
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set_property IOSTANDARD LVCMOS33 [get_ports led3]
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#UART
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set_property PACKAGE_PIN N20 [get_ports uart_tx]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
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set_property PACKAGE_PIN U20 [get_ports uart_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]
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#EEPROM
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set_property PACKAGE_PIN P16 [get_ports eeprom_scl]
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set_property IOSTANDARD LVCMOS33 [get_ports eeprom_scl]
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set_property PACKAGE_PIN P15 [get_ports eeprom_sda]
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set_property IOSTANDARD LVCMOS33 [get_ports eeprom_sda]
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#GPIO
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set_property PACKAGE_PIN K19 [get_ports gpio1]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio1]
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set_property PACKAGE_PIN F20 [get_ports gpio2]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio2]
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set_property PACKAGE_PIN J18 [get_ports gpio3]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio3]
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set_property PACKAGE_PIN L20 [get_ports gpio4]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio4]
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set_property PACKAGE_PIN L17 [get_ports gpio5]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio5]
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set_property PACKAGE_PIN M17 [get_ports gpio6]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio6]
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set_property PACKAGE_PIN K18 [get_ports gpio7]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio7]
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set_property PACKAGE_PIN L16 [get_ports gpio8]
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set_property IOSTANDARD LVCMOS33 [get_ports gpio8]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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from pyfpga.vivado import Vivado
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prj = Vivado(odir=f'./build')
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prj.set_part('xc7z010-2-clg400')
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prj.add_param('FREQ', '125000000')
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prj.add_cons('timing.xdc')
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prj.add_cons('pin.xdc')
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prj.add_param('SECS', '1')
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prj.add_include('./')
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prj.add_vlog('*.v')
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prj.add_vlog('./design_1/design_1.bd')
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prj.set_top('TOP')
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# prj.make()
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prj.prog()
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