From 8242950a58c26818b8da5909ad670d77176bb56c Mon Sep 17 00:00:00 2001
From: jrahmeh <joe.rahmeh@gmail.com>
Date: Tue, 13 Aug 2019 15:30:00 -0500
Subject: [PATCH] Fixed branch numbers

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index cf9f394..4edc08a 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
-# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
+# SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
 
-This repository contains the SweRV Core<sup>TM</sup> 1.1.1 design RTL. The previous version can be found in [branch 1.0,](https://github.com/chipsalliance/Cores-SweRV/tree/1.0)
+This repository contains the SweRV Core<sup>TM</sup> 1.2 design RTL. The previous version can be found in [branch 1.1.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.1)
 The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M).
 
 ## License