diff --git a/fpga/xc7z010/led.v b/fpga/xc7z010/led.v
index 35bace8..6b1fad9 100644
--- a/fpga/xc7z010/led.v
+++ b/fpga/xc7z010/led.v
@@ -3,11 +3,11 @@ module led(
 	output reg  led     // led 输出(高电平有效)
 );
 
-localparam  MAX_DELAY_CNT = 1000000,
+localparam  MAX_DELAY_CNT = 50000000,
             CYCLE_NUMBER  = 100;  //占空比分为0~100个级别
 
 reg myclk;
-reg [23:0] delay_cnt;
+reg [31:0] delay_cnt;
 reg [7:0] current_cycle;
 reg flag;
 reg [7:0] cycle;
@@ -18,8 +18,8 @@ always@(posedge clk) begin
 	if(delay_cnt < MAX_DELAY_CNT)
 		delay_cnt <= delay_cnt + 1'b1;
 	else begin
-		delay_cnt <= 24'd1;
-		myclk <= ~myclk;
+		delay_cnt <= 32'd1;
+		myclk <= ~myclk;  // 100Mhz
 	end
 end
 
@@ -52,10 +52,17 @@ always@(posedge clk)
 //--------------------------------------------------------
 // cycle小于current_cycle的时候是低电平
 // cycle大于current_cycle并且小于CYCLE_NUMBER的时候是高电平
+// always@(posedge clk)
+// 	if((cycle == CYCLE_NUMBER) && (current_cycle != 0))
+// 		led <= 1'b1;
+// 	else if(cycle < current_cycle)
+// 		led <= 1'b1;
+// 	else
+// 		led <= 1'b0;
+
+
 always@(posedge clk)
-	if((cycle == CYCLE_NUMBER) && (current_cycle != 0))
-		led <= 1'b1;
-	else if(cycle < current_cycle)
+	if((delay_cnt[20:14] ==0) && myclk)
 		led <= 1'b1;
 	else
 		led <= 1'b0;