From 853d12f17c75afb297df582912395b928951f692 Mon Sep 17 00:00:00 2001
From: colin <lianghongkey@gmail.com>
Date: Wed, 2 Feb 2022 03:34:37 +0000
Subject: [PATCH] Init to abstract accelerator project

---
 .gitignore => Cores-SweRV/.gitignore                |   0
 .travis.yml => Cores-SweRV/.travis.yml              |   0
 LICENSE => Cores-SweRV/LICENSE                      |   0
 README.md => Cores-SweRV/README.md                  |   0
 {configs => Cores-SweRV/configs}/README.md          |   0
 {configs => Cores-SweRV/configs}/swerv.config       |   0
 .../configs}/swerv_config_gen.py                    |   0
 {demo => Cores-SweRV/demo}/Readme.md                |   0
 {demo => Cores-SweRV/demo}/helloworld/Makefile      |   0
 {demo => Cores-SweRV/demo}/helloworld/Readme.md     |   0
 {demo => Cores-SweRV/demo}/helloworld/hello_world.c |   0
 {demo => Cores-SweRV/demo}/helloworld/hello_world.s |   0
 {demo => Cores-SweRV/demo}/helloworld/link.ld       |   0
 .../demo}/helloworld/test_soc_top.cpp               |   0
 {demo => Cores-SweRV/demo}/jtag/Makefile            |   0
 {demo => Cores-SweRV/demo}/jtag/Readmd.md           |   0
 {demo => Cores-SweRV/demo}/jtag/gdbinit             |   0
 {demo => Cores-SweRV/demo}/jtag/jtag.s              |   0
 {demo => Cores-SweRV/demo}/jtag/link.ld             |   0
 {demo => Cores-SweRV/demo}/jtag/swerv.cfg           |   0
 {demo => Cores-SweRV/demo}/jtag/test_soc_top.cpp    |   0
 {design => Cores-SweRV/design}/dbg/dbg.sv           |   0
 {design => Cores-SweRV/design}/dec/cdecode          |   0
 {design => Cores-SweRV/design}/dec/csrdecode        |   0
 {design => Cores-SweRV/design}/dec/dec.sv           |   0
 .../design}/dec/dec_decode_ctl.sv                   |   0
 {design => Cores-SweRV/design}/dec/dec_gpr_ctl.sv   |   0
 {design => Cores-SweRV/design}/dec/dec_ib_ctl.sv    |   0
 {design => Cores-SweRV/design}/dec/dec_tlu_ctl.sv   |   0
 {design => Cores-SweRV/design}/dec/dec_trigger.sv   |   0
 {design => Cores-SweRV/design}/dec/decode           |   0
 {design => Cores-SweRV/design}/dma_ctrl.sv          |   0
 .../design}/dmi/dmi_jtag_to_core_sync.v             |   0
 {design => Cores-SweRV/design}/dmi/dmi_wrapper.v    |   0
 {design => Cores-SweRV/design}/dmi/rvjtag_tap.sv    |   0
 {design => Cores-SweRV/design}/exu/exu.sv           |   0
 {design => Cores-SweRV/design}/exu/exu_alu_ctl.sv   |   0
 {design => Cores-SweRV/design}/exu/exu_div_ctl.sv   |   0
 {design => Cores-SweRV/design}/exu/exu_mul_ctl.sv   |   0
 {design => Cores-SweRV/design}/flist.questa         |   0
 {design => Cores-SweRV/design}/ifu/ifu.sv           |   0
 {design => Cores-SweRV/design}/ifu/ifu_aln_ctl.sv   |   0
 {design => Cores-SweRV/design}/ifu/ifu_bp_ctl.sv    |   0
 .../design}/ifu/ifu_compress_ctl.sv                 |   0
 {design => Cores-SweRV/design}/ifu/ifu_ic_mem.sv    |   0
 {design => Cores-SweRV/design}/ifu/ifu_iccm_mem.sv  |   0
 {design => Cores-SweRV/design}/ifu/ifu_ifc_ctl.sv   |   0
 {design => Cores-SweRV/design}/ifu/ifu_mem_ctl.sv   |   0
 {design => Cores-SweRV/design}/include/build.h      |   0
 {design => Cores-SweRV/design}/include/global.h     |   0
 .../design}/include/swerv_types.sv                  |   0
 {design => Cores-SweRV/design}/lib/ahb_to_axi4.sv   |   0
 {design => Cores-SweRV/design}/lib/axi4_to_ahb.sv   |   0
 {design => Cores-SweRV/design}/lib/beh_lib.sv       |   0
 {design => Cores-SweRV/design}/lib/mem_lib.sv       |   0
 {design => Cores-SweRV/design}/lib/svci_to_axi4.sv  |   0
 {design => Cores-SweRV/design}/lsu/lsu.sv           |   0
 {design => Cores-SweRV/design}/lsu/lsu_addrcheck.sv |   0
 .../design}/lsu/lsu_bus_buffer.sv                   |   0
 {design => Cores-SweRV/design}/lsu/lsu_bus_intf.sv  |   0
 {design => Cores-SweRV/design}/lsu/lsu_clkdomain.sv |   0
 {design => Cores-SweRV/design}/lsu/lsu_dccm_ctl.sv  |   0
 {design => Cores-SweRV/design}/lsu/lsu_dccm_mem.sv  |   0
 {design => Cores-SweRV/design}/lsu/lsu_ecc.sv       |   0
 {design => Cores-SweRV/design}/lsu/lsu_lsc_ctl.sv   |   0
 {design => Cores-SweRV/design}/lsu/lsu_stbuf.sv     |   0
 {design => Cores-SweRV/design}/lsu/lsu_trigger.sv   |   0
 {design => Cores-SweRV/design}/mem.sv               |   0
 {design => Cores-SweRV/design}/pic_ctrl.sv          |   0
 {design => Cores-SweRV/design}/swerv.sv             |   0
 {design => Cores-SweRV/design}/swerv_wrapper.sv     |   0
 {docs => Cores-SweRV/docs}/README.md                |   0
 {docs => Cores-SweRV/docs}/RISC-V_SweRV_EH1_PRM.pdf | Bin
 .../docs}/SweRV core roadmap white paper.pdf        | Bin
 .../docs}/SweRV_CoreMark_Benchmarking.pdf           | Bin
 release-notes.md => Cores-SweRV/release-notes.md    |   0
 {soc => Cores-SweRV/soc}/JSON.pm                    |   0
 {soc => Cores-SweRV/soc}/Makefile                   |   0
 {soc => Cores-SweRV/soc}/ahb_sif.sv                 |   0
 {soc => Cores-SweRV/soc}/axi_lsu_dma_bridge.sv      |   0
 {soc => Cores-SweRV/soc}/dasm.svi                   |   0
 {soc => Cores-SweRV/soc}/dpi/common/tcp_server.c    |   0
 {soc => Cores-SweRV/soc}/dpi/common/tcp_server.h    |   0
 {soc => Cores-SweRV/soc}/dpi/jtagdpi/jtagdpi.c      |   0
 {soc => Cores-SweRV/soc}/dpi/jtagdpi/jtagdpi.h      |   0
 {soc => Cores-SweRV/soc}/dpi/jtagdpi/jtagdpi.sv     |   0
 {soc => Cores-SweRV/soc}/soc.mk                     |   0
 {soc => Cores-SweRV/soc}/soc_top.sv                 |   0
 {soc => Cores-SweRV/soc}/swerv.config               |   0
 swerv.core => Cores-SweRV/swerv.core                |   0
 {testbench => Cores-SweRV/testbench}/ahb_sif.sv     |   0
 {testbench => Cores-SweRV/testbench}/asm/cmark.c    |   0
 {testbench => Cores-SweRV/testbench}/asm/cmark.mki  |   0
 .../testbench}/asm/cmark_dccm.c                     |   0
 .../testbench}/asm/cmark_dccm.ld                    |   0
 .../testbench}/asm/cmark_dccm.mki                   |   0
 .../testbench}/asm/cmark_iccm.c                     |   0
 .../testbench}/asm/cmark_iccm.ld                    |   0
 .../testbench}/asm/cmark_iccm.mki                   |   0
 {testbench => Cores-SweRV/testbench}/asm/crt0.s     |   0
 .../testbench}/asm/hello_world.s                    |   0
 .../testbench}/asm/hello_world_dccm.ld              |   0
 .../testbench}/asm/hello_world_dccm.s               |   0
 .../testbench}/asm/hello_world_iccm.ld              |   0
 .../testbench}/asm/hello_world_iccm.s               |   0
 {testbench => Cores-SweRV/testbench}/asm/printf.c   |   0
 .../testbench}/axi_lsu_dma_bridge.sv                |   0
 {testbench => Cores-SweRV/testbench}/dasm.svi       |   0
 {testbench => Cores-SweRV/testbench}/flist          |   0
 {testbench => Cores-SweRV/testbench}/hex/cmark.hex  |   0
 .../testbench}/hex/cmark_dccm.hex                   |   0
 .../testbench}/hex/cmark_iccm.hex                   |   0
 {testbench => Cores-SweRV/testbench}/hex/dhry.hex   |   0
 .../testbench}/hex/hello_world.hex                  |   0
 .../testbench}/hex/hello_world_dccm.hex             |   0
 .../testbench}/hex/hello_world_iccm.hex             |   0
 {testbench => Cores-SweRV/testbench}/input.tcl      |   0
 {testbench => Cores-SweRV/testbench}/link.ld        |   0
 {testbench => Cores-SweRV/testbench}/tb_top.sv      |   0
 .../testbench}/test_tb_top.cpp                      |   0
 .../testbench}/tests/dhry/README                    |   0
 .../testbench}/tests/dhry/crt0.s                    |   0
 .../testbench}/tests/dhry/dhry.h                    |   0
 .../testbench}/tests/dhry/dhry.ld                   |   0
 .../testbench}/tests/dhry/dhry.mki                  |   0
 .../testbench}/tests/dhry/dhry_1.c                  |   0
 .../testbench}/tests/dhry/dhry_2.c                  |   0
 .../testbench}/tests/dhry/printf.c                  |   0
 .../testbench}/tests/hello_world/Makefile           |   0
 .../testbench}/tests/hello_world/hello_world.s      |   0
 {tools => Cores-SweRV/tools}/JSON.pm                |   0
 {tools => Cores-SweRV/tools}/Makefile               |   0
 {tools => Cores-SweRV/tools}/addassign              |   0
 {tools => Cores-SweRV/tools}/coredecode             |   0
 {tools => Cores-SweRV/tools}/picmap                 |   0
 {tools => Cores-SweRV/tools}/smalldiv               |   0
 {tools => Cores-SweRV/tools}/unrollforverilator     |   0
 {tools => Cores-SweRV/tools}/vivado.tcl             |   0
 138 files changed, 0 insertions(+), 0 deletions(-)
 rename .gitignore => Cores-SweRV/.gitignore (100%)
 rename .travis.yml => Cores-SweRV/.travis.yml (100%)
 rename LICENSE => Cores-SweRV/LICENSE (100%)
 rename README.md => Cores-SweRV/README.md (100%)
 rename {configs => Cores-SweRV/configs}/README.md (100%)
 rename {configs => Cores-SweRV/configs}/swerv.config (100%)
 rename {configs => Cores-SweRV/configs}/swerv_config_gen.py (100%)
 rename {demo => Cores-SweRV/demo}/Readme.md (100%)
 rename {demo => Cores-SweRV/demo}/helloworld/Makefile (100%)
 rename {demo => Cores-SweRV/demo}/helloworld/Readme.md (100%)
 rename {demo => Cores-SweRV/demo}/helloworld/hello_world.c (100%)
 rename {demo => Cores-SweRV/demo}/helloworld/hello_world.s (100%)
 rename {demo => Cores-SweRV/demo}/helloworld/link.ld (100%)
 rename {demo => Cores-SweRV/demo}/helloworld/test_soc_top.cpp (100%)
 rename {demo => Cores-SweRV/demo}/jtag/Makefile (100%)
 rename {demo => Cores-SweRV/demo}/jtag/Readmd.md (100%)
 rename {demo => Cores-SweRV/demo}/jtag/gdbinit (100%)
 rename {demo => Cores-SweRV/demo}/jtag/jtag.s (100%)
 rename {demo => Cores-SweRV/demo}/jtag/link.ld (100%)
 rename {demo => Cores-SweRV/demo}/jtag/swerv.cfg (100%)
 rename {demo => Cores-SweRV/demo}/jtag/test_soc_top.cpp (100%)
 rename {design => Cores-SweRV/design}/dbg/dbg.sv (100%)
 rename {design => Cores-SweRV/design}/dec/cdecode (100%)
 rename {design => Cores-SweRV/design}/dec/csrdecode (100%)
 rename {design => Cores-SweRV/design}/dec/dec.sv (100%)
 rename {design => Cores-SweRV/design}/dec/dec_decode_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/dec/dec_gpr_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/dec/dec_ib_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/dec/dec_tlu_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/dec/dec_trigger.sv (100%)
 rename {design => Cores-SweRV/design}/dec/decode (100%)
 rename {design => Cores-SweRV/design}/dma_ctrl.sv (100%)
 rename {design => Cores-SweRV/design}/dmi/dmi_jtag_to_core_sync.v (100%)
 rename {design => Cores-SweRV/design}/dmi/dmi_wrapper.v (100%)
 rename {design => Cores-SweRV/design}/dmi/rvjtag_tap.sv (100%)
 rename {design => Cores-SweRV/design}/exu/exu.sv (100%)
 rename {design => Cores-SweRV/design}/exu/exu_alu_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/exu/exu_div_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/exu/exu_mul_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/flist.questa (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu.sv (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu_aln_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu_bp_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu_compress_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu_ic_mem.sv (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu_iccm_mem.sv (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu_ifc_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/ifu/ifu_mem_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/include/build.h (100%)
 rename {design => Cores-SweRV/design}/include/global.h (100%)
 rename {design => Cores-SweRV/design}/include/swerv_types.sv (100%)
 rename {design => Cores-SweRV/design}/lib/ahb_to_axi4.sv (100%)
 rename {design => Cores-SweRV/design}/lib/axi4_to_ahb.sv (100%)
 rename {design => Cores-SweRV/design}/lib/beh_lib.sv (100%)
 rename {design => Cores-SweRV/design}/lib/mem_lib.sv (100%)
 rename {design => Cores-SweRV/design}/lib/svci_to_axi4.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_addrcheck.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_bus_buffer.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_bus_intf.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_clkdomain.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_dccm_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_dccm_mem.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_ecc.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_lsc_ctl.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_stbuf.sv (100%)
 rename {design => Cores-SweRV/design}/lsu/lsu_trigger.sv (100%)
 rename {design => Cores-SweRV/design}/mem.sv (100%)
 rename {design => Cores-SweRV/design}/pic_ctrl.sv (100%)
 rename {design => Cores-SweRV/design}/swerv.sv (100%)
 rename {design => Cores-SweRV/design}/swerv_wrapper.sv (100%)
 rename {docs => Cores-SweRV/docs}/README.md (100%)
 rename {docs => Cores-SweRV/docs}/RISC-V_SweRV_EH1_PRM.pdf (100%)
 rename {docs => Cores-SweRV/docs}/SweRV core roadmap white paper.pdf (100%)
 rename {docs => Cores-SweRV/docs}/SweRV_CoreMark_Benchmarking.pdf (100%)
 rename release-notes.md => Cores-SweRV/release-notes.md (100%)
 rename {soc => Cores-SweRV/soc}/JSON.pm (100%)
 rename {soc => Cores-SweRV/soc}/Makefile (100%)
 rename {soc => Cores-SweRV/soc}/ahb_sif.sv (100%)
 rename {soc => Cores-SweRV/soc}/axi_lsu_dma_bridge.sv (100%)
 rename {soc => Cores-SweRV/soc}/dasm.svi (100%)
 rename {soc => Cores-SweRV/soc}/dpi/common/tcp_server.c (100%)
 rename {soc => Cores-SweRV/soc}/dpi/common/tcp_server.h (100%)
 rename {soc => Cores-SweRV/soc}/dpi/jtagdpi/jtagdpi.c (100%)
 rename {soc => Cores-SweRV/soc}/dpi/jtagdpi/jtagdpi.h (100%)
 rename {soc => Cores-SweRV/soc}/dpi/jtagdpi/jtagdpi.sv (100%)
 rename {soc => Cores-SweRV/soc}/soc.mk (100%)
 rename {soc => Cores-SweRV/soc}/soc_top.sv (100%)
 rename {soc => Cores-SweRV/soc}/swerv.config (100%)
 rename swerv.core => Cores-SweRV/swerv.core (100%)
 rename {testbench => Cores-SweRV/testbench}/ahb_sif.sv (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark.c (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark.mki (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark_dccm.c (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark_dccm.ld (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark_dccm.mki (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark_iccm.c (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark_iccm.ld (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/cmark_iccm.mki (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/crt0.s (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/hello_world.s (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/hello_world_dccm.ld (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/hello_world_dccm.s (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/hello_world_iccm.ld (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/hello_world_iccm.s (100%)
 rename {testbench => Cores-SweRV/testbench}/asm/printf.c (100%)
 rename {testbench => Cores-SweRV/testbench}/axi_lsu_dma_bridge.sv (100%)
 rename {testbench => Cores-SweRV/testbench}/dasm.svi (100%)
 rename {testbench => Cores-SweRV/testbench}/flist (100%)
 rename {testbench => Cores-SweRV/testbench}/hex/cmark.hex (100%)
 rename {testbench => Cores-SweRV/testbench}/hex/cmark_dccm.hex (100%)
 rename {testbench => Cores-SweRV/testbench}/hex/cmark_iccm.hex (100%)
 rename {testbench => Cores-SweRV/testbench}/hex/dhry.hex (100%)
 rename {testbench => Cores-SweRV/testbench}/hex/hello_world.hex (100%)
 rename {testbench => Cores-SweRV/testbench}/hex/hello_world_dccm.hex (100%)
 rename {testbench => Cores-SweRV/testbench}/hex/hello_world_iccm.hex (100%)
 rename {testbench => Cores-SweRV/testbench}/input.tcl (100%)
 rename {testbench => Cores-SweRV/testbench}/link.ld (100%)
 rename {testbench => Cores-SweRV/testbench}/tb_top.sv (100%)
 rename {testbench => Cores-SweRV/testbench}/test_tb_top.cpp (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/README (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/crt0.s (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/dhry.h (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/dhry.ld (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/dhry.mki (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/dhry_1.c (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/dhry_2.c (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/dhry/printf.c (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/hello_world/Makefile (100%)
 rename {testbench => Cores-SweRV/testbench}/tests/hello_world/hello_world.s (100%)
 rename {tools => Cores-SweRV/tools}/JSON.pm (100%)
 rename {tools => Cores-SweRV/tools}/Makefile (100%)
 rename {tools => Cores-SweRV/tools}/addassign (100%)
 rename {tools => Cores-SweRV/tools}/coredecode (100%)
 rename {tools => Cores-SweRV/tools}/picmap (100%)
 rename {tools => Cores-SweRV/tools}/smalldiv (100%)
 rename {tools => Cores-SweRV/tools}/unrollforverilator (100%)
 rename {tools => Cores-SweRV/tools}/vivado.tcl (100%)

diff --git a/.gitignore b/Cores-SweRV/.gitignore
similarity index 100%
rename from .gitignore
rename to Cores-SweRV/.gitignore
diff --git a/.travis.yml b/Cores-SweRV/.travis.yml
similarity index 100%
rename from .travis.yml
rename to Cores-SweRV/.travis.yml
diff --git a/LICENSE b/Cores-SweRV/LICENSE
similarity index 100%
rename from LICENSE
rename to Cores-SweRV/LICENSE
diff --git a/README.md b/Cores-SweRV/README.md
similarity index 100%
rename from README.md
rename to Cores-SweRV/README.md
diff --git a/configs/README.md b/Cores-SweRV/configs/README.md
similarity index 100%
rename from configs/README.md
rename to Cores-SweRV/configs/README.md
diff --git a/configs/swerv.config b/Cores-SweRV/configs/swerv.config
similarity index 100%
rename from configs/swerv.config
rename to Cores-SweRV/configs/swerv.config
diff --git a/configs/swerv_config_gen.py b/Cores-SweRV/configs/swerv_config_gen.py
similarity index 100%
rename from configs/swerv_config_gen.py
rename to Cores-SweRV/configs/swerv_config_gen.py
diff --git a/demo/Readme.md b/Cores-SweRV/demo/Readme.md
similarity index 100%
rename from demo/Readme.md
rename to Cores-SweRV/demo/Readme.md
diff --git a/demo/helloworld/Makefile b/Cores-SweRV/demo/helloworld/Makefile
similarity index 100%
rename from demo/helloworld/Makefile
rename to Cores-SweRV/demo/helloworld/Makefile
diff --git a/demo/helloworld/Readme.md b/Cores-SweRV/demo/helloworld/Readme.md
similarity index 100%
rename from demo/helloworld/Readme.md
rename to Cores-SweRV/demo/helloworld/Readme.md
diff --git a/demo/helloworld/hello_world.c b/Cores-SweRV/demo/helloworld/hello_world.c
similarity index 100%
rename from demo/helloworld/hello_world.c
rename to Cores-SweRV/demo/helloworld/hello_world.c
diff --git a/demo/helloworld/hello_world.s b/Cores-SweRV/demo/helloworld/hello_world.s
similarity index 100%
rename from demo/helloworld/hello_world.s
rename to Cores-SweRV/demo/helloworld/hello_world.s
diff --git a/demo/helloworld/link.ld b/Cores-SweRV/demo/helloworld/link.ld
similarity index 100%
rename from demo/helloworld/link.ld
rename to Cores-SweRV/demo/helloworld/link.ld
diff --git a/demo/helloworld/test_soc_top.cpp b/Cores-SweRV/demo/helloworld/test_soc_top.cpp
similarity index 100%
rename from demo/helloworld/test_soc_top.cpp
rename to Cores-SweRV/demo/helloworld/test_soc_top.cpp
diff --git a/demo/jtag/Makefile b/Cores-SweRV/demo/jtag/Makefile
similarity index 100%
rename from demo/jtag/Makefile
rename to Cores-SweRV/demo/jtag/Makefile
diff --git a/demo/jtag/Readmd.md b/Cores-SweRV/demo/jtag/Readmd.md
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