From 85a510db1968aecf9d7f2cec3d51ecce100ded78 Mon Sep 17 00:00:00 2001
From: Joseph Rahmeh <joseph.rahmeh@wdc.com>
Date: Tue, 13 Aug 2019 12:43:09 -0700
Subject: [PATCH] Updated release notes.

---
 release-notes.md | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/release-notes.md b/release-notes.md
index bdd7661..f367b68 100644
--- a/release-notes.md
+++ b/release-notes.md
@@ -1,4 +1,4 @@
-# SweRV RISC-V Core<sup>TM</sup> 1.1.1 from Western Digital
+# SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
 ## Release Notes
 1. SWERV core RISCV compatibility improvements
     * The ebreak and ecall instructions are no longer counted in the MINSRET
@@ -9,6 +9,8 @@
 1. FPGA support: Add fpga_optimize option to swerv.config which
    eliminates over 90% of clock-gating enabling faster FPGA
    simulation.
+   
+1. Usability: Untabified all the verilog files.
 
 # SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
 ## Release Notes