From 902f44a21cab987036057a28a13794054958a277 Mon Sep 17 00:00:00 2001 From: colin Date: Mon, 23 May 2022 14:45:23 +0000 Subject: [PATCH] Default use axi4 without ahb_lite. --- Flow/demo/Makefile | 2 +- Flow/design/dec/el2_dec_tlu_ctl.sv | 29 +- Flow/design/el2_swerv.sv | 390 +++++--------------------- Flow/design/el2_swerv_wrapper.sv | 254 ----------------- Flow/design/lsu/el2_lsu_bus_buffer.sv | 2 +- Flow/soc/swerv.config | 86 +----- 6 files changed, 87 insertions(+), 676 deletions(-) diff --git a/Flow/demo/Makefile b/Flow/demo/Makefile index 9c01df5..c4145b2 100644 --- a/Flow/demo/Makefile +++ b/Flow/demo/Makefile @@ -31,7 +31,7 @@ clean: rm -rf build obj_dir swerv_define : - BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set build_axi4 + BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default ##################### Verilog Builds ##################################### diff --git a/Flow/design/dec/el2_dec_tlu_ctl.sv b/Flow/design/dec/el2_dec_tlu_ctl.sv index c61c0d2..c02d1ff 100644 --- a/Flow/design/dec/el2_dec_tlu_ctl.sv +++ b/Flow/design/dec/el2_dec_tlu_ctl.sv @@ -1899,23 +1899,18 @@ else begin ); // flip poweron value of bit 6 for AXI build - if (pt.BUILD_AXI4 == 1) begin : axi4 - // flip poweron valid of bit 12 - assign mfdc_ns[15:0] = { - ~dec_csr_wrdata_r[18:16], - dec_csr_wrdata_r[12], - dec_csr_wrdata_r[11:7], - ~dec_csr_wrdata_r[6], - dec_csr_wrdata_r[5:0] - }; - assign mfdc[18:0] = { - ~mfdc_int[15:13], 3'b0, mfdc_int[12], mfdc_int[11:7], ~mfdc_int[6], mfdc_int[5:0] - }; - end else begin - // flip poweron valid of bit 12 - assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12:0]}; - assign mfdc[18:0] = {~mfdc_int[15:13], 3'b0, mfdc_int[12:0]}; - end + // flip poweron valid of bit 12 + assign mfdc_ns[15:0] = { + ~dec_csr_wrdata_r[18:16], + dec_csr_wrdata_r[12], + dec_csr_wrdata_r[11:7], + ~dec_csr_wrdata_r[6], + dec_csr_wrdata_r[5:0] + }; + assign mfdc[18:0] = { + ~mfdc_int[15:13], 3'b0, mfdc_int[12], mfdc_int[11:7], ~mfdc_int[6], mfdc_int[5:0] + }; + assign dec_tlu_dma_qos_prty[2:0] = mfdc[18:16]; diff --git a/Flow/design/el2_swerv.sv b/Flow/design/el2_swerv.sv index ea08dd6..1786bfa 100644 --- a/Flow/design/el2_swerv.sv +++ b/Flow/design/el2_swerv.sv @@ -983,345 +983,85 @@ module el2_swerv .* ); - if (pt.BUILD_AHB_LITE == 1) begin : Gen_AXI_To_AHB - - // AXI4 -> AHB Gasket for LSU - axi4_to_ahb #( - .pt (pt), - .TAG(pt.LSU_BUS_TAG) - ) lsu_axi4_to_ahb ( - - .clk(free_l2clk), - .free_clk(free_clk), - .rst_l(core_rst_l), - .clk_override(dec_tlu_bus_clk_override), - .bus_clk_en(lsu_bus_clk_en), - .dec_tlu_force_halt(dec_tlu_force_halt), - - // AXI Write Channels - .axi_awvalid(lsu_axi_awvalid), - .axi_awready(lsu_axi_awready_ahb), - .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]), - .axi_awaddr(lsu_axi_awaddr[31:0]), - .axi_awsize(lsu_axi_awsize[2:0]), - .axi_awprot(lsu_axi_awprot[2:0]), - - .axi_wvalid(lsu_axi_wvalid), - .axi_wready(lsu_axi_wready_ahb), - .axi_wdata (lsu_axi_wdata[63:0]), - .axi_wstrb (lsu_axi_wstrb[7:0]), - .axi_wlast (lsu_axi_wlast), - - .axi_bvalid(lsu_axi_bvalid_ahb), - .axi_bready(lsu_axi_bready), - .axi_bresp(lsu_axi_bresp_ahb[1:0]), - .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]), - - // AXI Read Channels - .axi_arvalid(lsu_axi_arvalid), - .axi_arready(lsu_axi_arready_ahb), - .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]), - .axi_araddr(lsu_axi_araddr[31:0]), - .axi_arsize(lsu_axi_arsize[2:0]), - .axi_arprot(lsu_axi_arprot[2:0]), - - .axi_rvalid(lsu_axi_rvalid_ahb), - .axi_rready(lsu_axi_rready), - .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]), - .axi_rdata(lsu_axi_rdata_ahb[63:0]), - .axi_rresp(lsu_axi_rresp_ahb[1:0]), - .axi_rlast(lsu_axi_rlast_ahb), - - // AHB-LITE signals - .ahb_haddr(lsu_haddr[31:0]), - .ahb_hburst(lsu_hburst), - .ahb_hmastlock(lsu_hmastlock), - .ahb_hprot(lsu_hprot[3:0]), - .ahb_hsize(lsu_hsize[2:0]), - .ahb_htrans(lsu_htrans[1:0]), - .ahb_hwrite(lsu_hwrite), - .ahb_hwdata(lsu_hwdata[63:0]), - - .ahb_hrdata(lsu_hrdata[63:0]), - .ahb_hready(lsu_hready), - .ahb_hresp (lsu_hresp), - - .* - ); - - axi4_to_ahb #( - .pt (pt), - .TAG(pt.IFU_BUS_TAG) - ) ifu_axi4_to_ahb ( - .clk(free_l2clk), - .free_clk(free_clk), - .rst_l(core_rst_l), - .clk_override(dec_tlu_bus_clk_override), - .bus_clk_en(ifu_bus_clk_en), - .dec_tlu_force_halt(dec_tlu_force_halt), - - // AHB-Lite signals - .ahb_haddr(haddr[31:0]), - .ahb_hburst(hburst), - .ahb_hmastlock(hmastlock), - .ahb_hprot(hprot[3:0]), - .ahb_hsize(hsize[2:0]), - .ahb_htrans(htrans[1:0]), - .ahb_hwrite(hwrite), - .ahb_hwdata(hwdata_nc[63:0]), - - .ahb_hrdata(hrdata[63:0]), - .ahb_hready(hready), - .ahb_hresp (hresp), - - // AXI Write Channels - .axi_awvalid(ifu_axi_awvalid), - .axi_awready(ifu_axi_awready_ahb), - .axi_awid(ifu_axi_awid[pt.IFU_BUS_TAG-1:0]), - .axi_awaddr(ifu_axi_awaddr[31:0]), - .axi_awsize(ifu_axi_awsize[2:0]), - .axi_awprot(ifu_axi_awprot[2:0]), - - .axi_wvalid(ifu_axi_wvalid), - .axi_wready(ifu_axi_wready_ahb), - .axi_wdata (ifu_axi_wdata[63:0]), - .axi_wstrb (ifu_axi_wstrb[7:0]), - .axi_wlast (ifu_axi_wlast), - - .axi_bvalid(ifu_axi_bvalid_ahb), - .axi_bready(1'b1), - .axi_bresp(ifu_axi_bresp_ahb[1:0]), - .axi_bid(ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0]), - - // AXI Read Channels - .axi_arvalid(ifu_axi_arvalid), - .axi_arready(ifu_axi_arready_ahb), - .axi_arid(ifu_axi_arid[pt.IFU_BUS_TAG-1:0]), - .axi_araddr(ifu_axi_araddr[31:0]), - .axi_arsize(ifu_axi_arsize[2:0]), - .axi_arprot(ifu_axi_arprot[2:0]), - - .axi_rvalid(ifu_axi_rvalid_ahb), - .axi_rready(ifu_axi_rready), - .axi_rid(ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0]), - .axi_rdata(ifu_axi_rdata_ahb[63:0]), - .axi_rresp(ifu_axi_rresp_ahb[1:0]), - .axi_rlast(ifu_axi_rlast_ahb), - .* - ); - - // AXI4 -> AHB Gasket for System Bus - axi4_to_ahb #( - .pt (pt), - .TAG(pt.SB_BUS_TAG) - ) sb_axi4_to_ahb ( - .clk(free_l2clk), - .free_clk(free_clk), - .rst_l(dbg_rst_l), - .clk_override(dec_tlu_bus_clk_override), - .bus_clk_en(dbg_bus_clk_en), - .dec_tlu_force_halt(1'b0), - - // AXI Write Channels - .axi_awvalid(sb_axi_awvalid), - .axi_awready(sb_axi_awready_ahb), - .axi_awid(sb_axi_awid[pt.SB_BUS_TAG-1:0]), - .axi_awaddr(sb_axi_awaddr[31:0]), - .axi_awsize(sb_axi_awsize[2:0]), - .axi_awprot(sb_axi_awprot[2:0]), - - .axi_wvalid(sb_axi_wvalid), - .axi_wready(sb_axi_wready_ahb), - .axi_wdata (sb_axi_wdata[63:0]), - .axi_wstrb (sb_axi_wstrb[7:0]), - .axi_wlast (sb_axi_wlast), - - .axi_bvalid(sb_axi_bvalid_ahb), - .axi_bready(sb_axi_bready), - .axi_bresp(sb_axi_bresp_ahb[1:0]), - .axi_bid(sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0]), - - // AXI Read Channels - .axi_arvalid(sb_axi_arvalid), - .axi_arready(sb_axi_arready_ahb), - .axi_arid(sb_axi_arid[pt.SB_BUS_TAG-1:0]), - .axi_araddr(sb_axi_araddr[31:0]), - .axi_arsize(sb_axi_arsize[2:0]), - .axi_arprot(sb_axi_arprot[2:0]), - - .axi_rvalid(sb_axi_rvalid_ahb), - .axi_rready(sb_axi_rready), - .axi_rid(sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0]), - .axi_rdata(sb_axi_rdata_ahb[63:0]), - .axi_rresp(sb_axi_rresp_ahb[1:0]), - .axi_rlast(sb_axi_rlast_ahb), - // AHB-LITE signals - .ahb_haddr(sb_haddr[31:0]), - .ahb_hburst(sb_hburst), - .ahb_hmastlock(sb_hmastlock), - .ahb_hprot(sb_hprot[3:0]), - .ahb_hsize(sb_hsize[2:0]), - .ahb_htrans(sb_htrans[1:0]), - .ahb_hwrite(sb_hwrite), - .ahb_hwdata(sb_hwdata[63:0]), - - .ahb_hrdata(sb_hrdata[63:0]), - .ahb_hready(sb_hready), - .ahb_hresp (sb_hresp), - - .* - ); - - //AHB -> AXI4 Gasket for DMA - ahb_to_axi4 #( - .pt (pt), - .TAG(pt.DMA_BUS_TAG) - ) dma_ahb_to_axi4 ( - .clk(free_l2clk), - .rst_l(core_rst_l), - .clk_override(dec_tlu_bus_clk_override), - .bus_clk_en(dma_bus_clk_en), - - // AXI Write Channels - .axi_awvalid(dma_axi_awvalid_ahb), - .axi_awready(dma_axi_awready), - .axi_awid(dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0]), - .axi_awaddr(dma_axi_awaddr_ahb[31:0]), - .axi_awsize(dma_axi_awsize_ahb[2:0]), - .axi_awprot(dma_axi_awprot_ahb[2:0]), - .axi_awlen(dma_axi_awlen_ahb[7:0]), - .axi_awburst(dma_axi_awburst_ahb[1:0]), - - .axi_wvalid(dma_axi_wvalid_ahb), - .axi_wready(dma_axi_wready), - .axi_wdata (dma_axi_wdata_ahb[63:0]), - .axi_wstrb (dma_axi_wstrb_ahb[7:0]), - .axi_wlast (dma_axi_wlast_ahb), - - .axi_bvalid(dma_axi_bvalid), - .axi_bready(dma_axi_bready_ahb), - .axi_bresp(dma_axi_bresp[1:0]), - .axi_bid(dma_axi_bid[pt.DMA_BUS_TAG-1:0]), - - // AXI Read Channels - .axi_arvalid(dma_axi_arvalid_ahb), - .axi_arready(dma_axi_arready), - .axi_arid(dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0]), - .axi_araddr(dma_axi_araddr_ahb[31:0]), - .axi_arsize(dma_axi_arsize_ahb[2:0]), - .axi_arprot(dma_axi_arprot_ahb[2:0]), - .axi_arlen(dma_axi_arlen_ahb[7:0]), - .axi_arburst(dma_axi_arburst_ahb[1:0]), - - .axi_rvalid(dma_axi_rvalid), - .axi_rready(dma_axi_rready_ahb), - .axi_rid(dma_axi_rid[pt.DMA_BUS_TAG-1:0]), - .axi_rdata(dma_axi_rdata[63:0]), - .axi_rresp(dma_axi_rresp[1:0]), - - // AHB signals - .ahb_haddr(dma_haddr[31:0]), - .ahb_hburst(dma_hburst), - .ahb_hmastlock(dma_hmastlock), - .ahb_hprot(dma_hprot[3:0]), - .ahb_hsize(dma_hsize[2:0]), - .ahb_htrans(dma_htrans[1:0]), - .ahb_hwrite(dma_hwrite), - .ahb_hwdata(dma_hwdata[63:0]), - - .ahb_hrdata(dma_hrdata[63:0]), - .ahb_hreadyout(dma_hreadyout), - .ahb_hresp(dma_hresp), - .ahb_hreadyin(dma_hreadyin), - .ahb_hsel(dma_hsel), - .* - ); - - end - // Drive the final AXI inputs - assign lsu_axi_awready_int = pt.BUILD_AHB_LITE ? lsu_axi_awready_ahb : lsu_axi_awready; - assign lsu_axi_wready_int = pt.BUILD_AHB_LITE ? lsu_axi_wready_ahb : lsu_axi_wready; - assign lsu_axi_bvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_bvalid_ahb : lsu_axi_bvalid; - assign lsu_axi_bready_int = pt.BUILD_AHB_LITE ? lsu_axi_bready_ahb : lsu_axi_bready; - assign lsu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0]; - assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_bid[pt.LSU_BUS_TAG-1:0]; - assign lsu_axi_arready_int = pt.BUILD_AHB_LITE ? lsu_axi_arready_ahb : lsu_axi_arready; - assign lsu_axi_rvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_rvalid_ahb : lsu_axi_rvalid; - assign lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_rid[pt.LSU_BUS_TAG-1:0]; - assign lsu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0]; - assign lsu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0]; - assign lsu_axi_rlast_int = pt.BUILD_AHB_LITE ? lsu_axi_rlast_ahb : lsu_axi_rlast; + assign lsu_axi_awready_int = lsu_axi_awready; + assign lsu_axi_wready_int = lsu_axi_wready; + assign lsu_axi_bvalid_int = lsu_axi_bvalid; + assign lsu_axi_bready_int = lsu_axi_bready; + assign lsu_axi_bresp_int[1:0] = lsu_axi_bresp[1:0]; + assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = lsu_axi_bid[pt.LSU_BUS_TAG-1:0]; + assign lsu_axi_arready_int = lsu_axi_arready; + assign lsu_axi_rvalid_int = lsu_axi_rvalid; + assign lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0] = lsu_axi_rid[pt.LSU_BUS_TAG-1:0]; + assign lsu_axi_rdata_int[63:0] = lsu_axi_rdata[63:0]; + assign lsu_axi_rresp_int[1:0] = lsu_axi_rresp[1:0]; + assign lsu_axi_rlast_int = lsu_axi_rlast; - assign ifu_axi_awready_int = pt.BUILD_AHB_LITE ? ifu_axi_awready_ahb : ifu_axi_awready; - assign ifu_axi_wready_int = pt.BUILD_AHB_LITE ? ifu_axi_wready_ahb : ifu_axi_wready; - assign ifu_axi_bvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_bvalid_ahb : ifu_axi_bvalid; - assign ifu_axi_bready_int = pt.BUILD_AHB_LITE ? ifu_axi_bready_ahb : ifu_axi_bready; - assign ifu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0]; - assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_bid[pt.IFU_BUS_TAG-1:0]; - assign ifu_axi_arready_int = pt.BUILD_AHB_LITE ? ifu_axi_arready_ahb : ifu_axi_arready; - assign ifu_axi_rvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_rvalid_ahb : ifu_axi_rvalid; - assign ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_rid[pt.IFU_BUS_TAG-1:0]; - assign ifu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0]; - assign ifu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0]; - assign ifu_axi_rlast_int = pt.BUILD_AHB_LITE ? ifu_axi_rlast_ahb : ifu_axi_rlast; + assign ifu_axi_awready_int = ifu_axi_awready; + assign ifu_axi_wready_int = ifu_axi_wready; + assign ifu_axi_bvalid_int = ifu_axi_bvalid; + assign ifu_axi_bready_int = ifu_axi_bready; + assign ifu_axi_bresp_int[1:0] = ifu_axi_bresp[1:0]; + assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = ifu_axi_bid[pt.IFU_BUS_TAG-1:0]; + assign ifu_axi_arready_int = ifu_axi_arready; + assign ifu_axi_rvalid_int = ifu_axi_rvalid; + assign ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0] = ifu_axi_rid[pt.IFU_BUS_TAG-1:0]; + assign ifu_axi_rdata_int[63:0] = ifu_axi_rdata[63:0]; + assign ifu_axi_rresp_int[1:0] = ifu_axi_rresp[1:0]; + assign ifu_axi_rlast_int = ifu_axi_rlast; - assign sb_axi_awready_int = pt.BUILD_AHB_LITE ? sb_axi_awready_ahb : sb_axi_awready; - assign sb_axi_wready_int = pt.BUILD_AHB_LITE ? sb_axi_wready_ahb : sb_axi_wready; - assign sb_axi_bvalid_int = pt.BUILD_AHB_LITE ? sb_axi_bvalid_ahb : sb_axi_bvalid; - assign sb_axi_bready_int = pt.BUILD_AHB_LITE ? sb_axi_bready_ahb : sb_axi_bready; - assign sb_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0]; - assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_bid[pt.SB_BUS_TAG-1:0]; - assign sb_axi_arready_int = pt.BUILD_AHB_LITE ? sb_axi_arready_ahb : sb_axi_arready; - assign sb_axi_rvalid_int = pt.BUILD_AHB_LITE ? sb_axi_rvalid_ahb : sb_axi_rvalid; - assign sb_axi_rid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_rid[pt.SB_BUS_TAG-1:0]; - assign sb_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0]; - assign sb_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0]; - assign sb_axi_rlast_int = pt.BUILD_AHB_LITE ? sb_axi_rlast_ahb : sb_axi_rlast; + assign sb_axi_awready_int = sb_axi_awready; + assign sb_axi_wready_int = sb_axi_wready; + assign sb_axi_bvalid_int = sb_axi_bvalid; + assign sb_axi_bready_int = sb_axi_bready; + assign sb_axi_bresp_int[1:0] = sb_axi_bresp[1:0]; + assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0] = sb_axi_bid[pt.SB_BUS_TAG-1:0]; + assign sb_axi_arready_int = sb_axi_arready; + assign sb_axi_rvalid_int = sb_axi_rvalid; + assign sb_axi_rid_int[pt.SB_BUS_TAG-1:0] = sb_axi_rid[pt.SB_BUS_TAG-1:0]; + assign sb_axi_rdata_int[63:0] = sb_axi_rdata[63:0]; + assign sb_axi_rresp_int[1:0] = sb_axi_rresp[1:0]; + assign sb_axi_rlast_int = sb_axi_rlast; - assign dma_axi_awvalid_int = pt.BUILD_AHB_LITE ? dma_axi_awvalid_ahb : dma_axi_awvalid; - assign dma_axi_awid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_awid[pt.DMA_BUS_TAG-1:0]; - assign dma_axi_awaddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0]; - assign dma_axi_awsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0]; - assign dma_axi_awprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0]; - assign dma_axi_awlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0]; - assign dma_axi_awburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0]; - assign dma_axi_wvalid_int = pt.BUILD_AHB_LITE ? dma_axi_wvalid_ahb : dma_axi_wvalid; - assign dma_axi_wdata_int[63:0] = pt.BUILD_AHB_LITE ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata; - assign dma_axi_wstrb_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0]; - assign dma_axi_wlast_int = pt.BUILD_AHB_LITE ? dma_axi_wlast_ahb : dma_axi_wlast; - assign dma_axi_bready_int = pt.BUILD_AHB_LITE ? dma_axi_bready_ahb : dma_axi_bready; - assign dma_axi_arvalid_int = pt.BUILD_AHB_LITE ? dma_axi_arvalid_ahb : dma_axi_arvalid; - assign dma_axi_arid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_arid[pt.DMA_BUS_TAG-1:0]; - assign dma_axi_araddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0]; - assign dma_axi_arsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0]; - assign dma_axi_arprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0]; - assign dma_axi_arlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0]; - assign dma_axi_arburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0]; - assign dma_axi_rready_int = pt.BUILD_AHB_LITE ? dma_axi_rready_ahb : dma_axi_rready; + assign dma_axi_awvalid_int = dma_axi_awvalid; + assign dma_axi_awid_int[pt.DMA_BUS_TAG-1:0] = dma_axi_awid[pt.DMA_BUS_TAG-1:0]; + assign dma_axi_awaddr_int[31:0] = dma_axi_awaddr[31:0]; + assign dma_axi_awsize_int[2:0] = dma_axi_awsize[2:0]; + assign dma_axi_awprot_int[2:0] = dma_axi_awprot[2:0]; + assign dma_axi_awlen_int[7:0] = dma_axi_awlen[7:0]; + assign dma_axi_awburst_int[1:0] = dma_axi_awburst[1:0]; + assign dma_axi_wvalid_int = dma_axi_wvalid; + assign dma_axi_wdata_int[63:0] = dma_axi_wdata; + assign dma_axi_wstrb_int[7:0] = dma_axi_wstrb[7:0]; + assign dma_axi_wlast_int = dma_axi_wlast; + assign dma_axi_bready_int = dma_axi_bready; + assign dma_axi_arvalid_int = dma_axi_arvalid; + assign dma_axi_arid_int[pt.DMA_BUS_TAG-1:0] = dma_axi_arid[pt.DMA_BUS_TAG-1:0]; + assign dma_axi_araddr_int[31:0] = dma_axi_araddr[31:0]; + assign dma_axi_arsize_int[2:0] = dma_axi_arsize[2:0]; + assign dma_axi_arprot_int[2:0] = dma_axi_arprot[2:0]; + assign dma_axi_arlen_int[7:0] = dma_axi_arlen[7:0]; + assign dma_axi_arburst_int[1:0] = dma_axi_arburst[1:0]; + assign dma_axi_rready_int = dma_axi_rready; - if (pt.BUILD_AHB_LITE == 1) begin - end // if (pt.BUILD_AHB_LITE == 1) + // unpack packet + // also need retires_p==3 + assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_insn_ip[31:0]; - // unpack packet - // also need retires_p==3 + assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_address_ip[31:0]; - assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_insn_ip[31:0]; + assign trace_rv_i_valid_ip = trace_rv_trace_pkt.trace_rv_i_valid_ip; - assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_address_ip[31:0]; + assign trace_rv_i_exception_ip = trace_rv_trace_pkt.trace_rv_i_exception_ip; - assign trace_rv_i_valid_ip = trace_rv_trace_pkt.trace_rv_i_valid_ip; + assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt.trace_rv_i_ecause_ip[4:0]; - assign trace_rv_i_exception_ip = trace_rv_trace_pkt.trace_rv_i_exception_ip; + assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt.trace_rv_i_interrupt_ip; - assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt.trace_rv_i_ecause_ip[4:0]; - - assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt.trace_rv_i_interrupt_ip; - - assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_tval_ip[31:0]; + assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_tval_ip[31:0]; diff --git a/Flow/design/el2_swerv_wrapper.sv b/Flow/design/el2_swerv_wrapper.sv index 26b4b17..68941e5 100644 --- a/Flow/design/el2_swerv_wrapper.sv +++ b/Flow/design/el2_swerv_wrapper.sv @@ -42,8 +42,6 @@ module el2_swerv_wrapper output logic trace_rv_i_interrupt_ip, output logic [31:0] trace_rv_i_tval_ip, - // Bus signals -`ifdef RV_BUILD_AXI4 //-------------------------- LSU AXI signals-------------------------- // AXI Write Channels output logic lsu_axi_awvalid, @@ -224,65 +222,7 @@ module el2_swerv_wrapper output logic [ 63:0] dma_axi_rdata, output logic [ 1:0] dma_axi_rresp, output logic dma_axi_rlast, -`endif -`ifdef RV_BUILD_AHB_LITE - //// AHB LITE BUS - output logic [31:0] haddr, - output logic [ 2:0] hburst, - output logic hmastlock, - output logic [ 3:0] hprot, - output logic [ 2:0] hsize, - output logic [ 1:0] htrans, - output logic hwrite, - - input logic [63:0] hrdata, - input logic hready, - input logic hresp, - - // LSU AHB Master - output logic [31:0] lsu_haddr, - output logic [ 2:0] lsu_hburst, - output logic lsu_hmastlock, - output logic [ 3:0] lsu_hprot, - output logic [ 2:0] lsu_hsize, - output logic [ 1:0] lsu_htrans, - output logic lsu_hwrite, - output logic [63:0] lsu_hwdata, - - input logic [63:0] lsu_hrdata, - input logic lsu_hready, - input logic lsu_hresp, - // Debug Syster Bus AHB - output logic [31:0] sb_haddr, - output logic [ 2:0] sb_hburst, - output logic sb_hmastlock, - output logic [ 3:0] sb_hprot, - output logic [ 2:0] sb_hsize, - output logic [ 1:0] sb_htrans, - output logic sb_hwrite, - output logic [63:0] sb_hwdata, - - input logic [63:0] sb_hrdata, - input logic sb_hready, - input logic sb_hresp, - - // DMA Slave - input logic dma_hsel, - input logic [31:0] dma_haddr, - input logic [ 2:0] dma_hburst, - input logic dma_hmastlock, - input logic [ 3:0] dma_hprot, - input logic [ 2:0] dma_hsize, - input logic [ 1:0] dma_htrans, - input logic dma_hwrite, - input logic [63:0] dma_hwdata, - input logic dma_hreadyin, - - output logic [63:0] dma_hrdata, - output logic dma_hreadyout, - output logic dma_hresp, -`endif // clk ratio signals input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface @@ -400,8 +340,6 @@ module el2_swerv_wrapper // zero out the signals not presented at the wrapper instantiation level -`ifdef RV_BUILD_AXI4 - //// AHB LITE BUS logic [31:0] haddr; logic [ 2:0] hburst; @@ -485,198 +423,6 @@ module el2_swerv_wrapper assign dma_hwdata[63:0] = '0; assign dma_hreadyin = '0; -`endif // `ifdef RV_BUILD_AXI4 - - -`ifdef RV_BUILD_AHB_LITE - wire lsu_axi_awvalid; - wire lsu_axi_awready; - wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid; - wire [ 31:0] lsu_axi_awaddr; - wire [ 3:0] lsu_axi_awregion; - wire [ 7:0] lsu_axi_awlen; - wire [ 2:0] lsu_axi_awsize; - wire [ 1:0] lsu_axi_awburst; - wire lsu_axi_awlock; - wire [ 3:0] lsu_axi_awcache; - wire [ 2:0] lsu_axi_awprot; - wire [ 3:0] lsu_axi_awqos; - - wire lsu_axi_wvalid; - wire lsu_axi_wready; - wire [ 63:0] lsu_axi_wdata; - wire [ 7:0] lsu_axi_wstrb; - wire lsu_axi_wlast; - - wire lsu_axi_bvalid; - wire lsu_axi_bready; - wire [ 1:0] lsu_axi_bresp; - wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid; - - // AXI Read Channels - wire lsu_axi_arvalid; - wire lsu_axi_arready; - wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid; - wire [ 31:0] lsu_axi_araddr; - wire [ 3:0] lsu_axi_arregion; - wire [ 7:0] lsu_axi_arlen; - wire [ 2:0] lsu_axi_arsize; - wire [ 1:0] lsu_axi_arburst; - wire lsu_axi_arlock; - wire [ 3:0] lsu_axi_arcache; - wire [ 2:0] lsu_axi_arprot; - wire [ 3:0] lsu_axi_arqos; - - wire lsu_axi_rvalid; - wire lsu_axi_rready; - wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid; - wire [ 63:0] lsu_axi_rdata; - wire [ 1:0] lsu_axi_rresp; - wire lsu_axi_rlast; - - //-------------------------- IFU AXI signals-------------------------- - // AXI Write Channels - wire ifu_axi_awvalid; - wire ifu_axi_awready; - wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid; - wire [ 31:0] ifu_axi_awaddr; - wire [ 3:0] ifu_axi_awregion; - wire [ 7:0] ifu_axi_awlen; - wire [ 2:0] ifu_axi_awsize; - wire [ 1:0] ifu_axi_awburst; - wire ifu_axi_awlock; - wire [ 3:0] ifu_axi_awcache; - wire [ 2:0] ifu_axi_awprot; - wire [ 3:0] ifu_axi_awqos; - - wire ifu_axi_wvalid; - wire ifu_axi_wready; - wire [ 63:0] ifu_axi_wdata; - wire [ 7:0] ifu_axi_wstrb; - wire ifu_axi_wlast; - - wire ifu_axi_bvalid; - wire ifu_axi_bready; - wire [ 1:0] ifu_axi_bresp; - wire [pt.IFU_BUS_TAG-1:0] ifu_axi_bid; - - // AXI Read Channels - wire ifu_axi_arvalid; - wire ifu_axi_arready; - wire [pt.IFU_BUS_TAG-1:0] ifu_axi_arid; - wire [ 31:0] ifu_axi_araddr; - wire [ 3:0] ifu_axi_arregion; - wire [ 7:0] ifu_axi_arlen; - wire [ 2:0] ifu_axi_arsize; - wire [ 1:0] ifu_axi_arburst; - wire ifu_axi_arlock; - wire [ 3:0] ifu_axi_arcache; - wire [ 2:0] ifu_axi_arprot; - wire [ 3:0] ifu_axi_arqos; - - wire ifu_axi_rvalid; - wire ifu_axi_rready; - wire [pt.IFU_BUS_TAG-1:0] ifu_axi_rid; - wire [ 63:0] ifu_axi_rdata; - wire [ 1:0] ifu_axi_rresp; - wire ifu_axi_rlast; - - //-------------------------- SB AXI signals-------------------------- - // AXI Write Channels - wire sb_axi_awvalid; - wire sb_axi_awready; - wire [ pt.SB_BUS_TAG-1:0] sb_axi_awid; - wire [ 31:0] sb_axi_awaddr; - wire [ 3:0] sb_axi_awregion; - wire [ 7:0] sb_axi_awlen; - wire [ 2:0] sb_axi_awsize; - wire [ 1:0] sb_axi_awburst; - wire sb_axi_awlock; - wire [ 3:0] sb_axi_awcache; - wire [ 2:0] sb_axi_awprot; - wire [ 3:0] sb_axi_awqos; - - wire sb_axi_wvalid; - wire sb_axi_wready; - wire [ 63:0] sb_axi_wdata; - wire [ 7:0] sb_axi_wstrb; - wire sb_axi_wlast; - - wire sb_axi_bvalid; - wire sb_axi_bready; - wire [ 1:0] sb_axi_bresp; - wire [ pt.SB_BUS_TAG-1:0] sb_axi_bid; - - // AXI Read Channels - wire sb_axi_arvalid; - wire sb_axi_arready; - wire [ pt.SB_BUS_TAG-1:0] sb_axi_arid; - wire [ 31:0] sb_axi_araddr; - wire [ 3:0] sb_axi_arregion; - wire [ 7:0] sb_axi_arlen; - wire [ 2:0] sb_axi_arsize; - wire [ 1:0] sb_axi_arburst; - wire sb_axi_arlock; - wire [ 3:0] sb_axi_arcache; - wire [ 2:0] sb_axi_arprot; - wire [ 3:0] sb_axi_arqos; - - wire sb_axi_rvalid; - wire sb_axi_rready; - wire [ pt.SB_BUS_TAG-1:0] sb_axi_rid; - wire [ 63:0] sb_axi_rdata; - wire [ 1:0] sb_axi_rresp; - wire sb_axi_rlast; - - //-------------------------- DMA AXI signals-------------------------- - // AXI Write Channels - wire dma_axi_awvalid; - wire dma_axi_awready; - wire [pt.DMA_BUS_TAG-1:0] dma_axi_awid; - wire [ 31:0] dma_axi_awaddr; - wire [ 2:0] dma_axi_awsize; - wire [ 2:0] dma_axi_awprot; - wire [ 7:0] dma_axi_awlen; - wire [ 1:0] dma_axi_awburst; - - - wire dma_axi_wvalid; - wire dma_axi_wready; - wire [ 63:0] dma_axi_wdata; - wire [ 7:0] dma_axi_wstrb; - wire dma_axi_wlast; - - wire dma_axi_bvalid; - wire dma_axi_bready; - wire [ 1:0] dma_axi_bresp; - wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid; - - // AXI Read Channels - wire dma_axi_arvalid; - wire dma_axi_arready; - wire [pt.DMA_BUS_TAG-1:0] dma_axi_arid; - wire [ 31:0] dma_axi_araddr; - wire [ 2:0] dma_axi_arsize; - wire [ 2:0] dma_axi_arprot; - wire [ 7:0] dma_axi_arlen; - wire [ 1:0] dma_axi_arburst; - - wire dma_axi_rvalid; - wire dma_axi_rready; - wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid; - wire [ 63:0] dma_axi_rdata; - wire [ 1:0] dma_axi_rresp; - wire dma_axi_rlast; - - // AXI - assign ifu_axi_awready = 1'b1; - assign ifu_axi_wready = 1'b1; - assign ifu_axi_bvalid = '0; - assign ifu_axi_bresp[1:0] = '0; - assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0; - -`endif // `ifdef RV_BUILD_AHB_LITE - logic dmi_reg_en; logic [ 6:0] dmi_reg_addr; logic dmi_reg_wr_en; diff --git a/Flow/design/lsu/el2_lsu_bus_buffer.sv b/Flow/design/lsu/el2_lsu_bus_buffer.sv index b0171c5..0e8c21f 100644 --- a/Flow/design/lsu/el2_lsu_bus_buffer.sv +++ b/Flow/design/lsu/el2_lsu_bus_buffer.sv @@ -411,7 +411,7 @@ module el2_lsu_bus_buffer // Load forwarding logic end //------------------------------------------------------------------------------ - assign bus_coalescing_disable = dec_tlu_wb_coalescing_disable | pt.BUILD_AHB_LITE; + assign bus_coalescing_disable = dec_tlu_wb_coalescing_disable; // Get the hi/lo byte enable assign ldst_byteen_r[3:0] = ({4{lsu_pkt_r.by}} & 4'b0001) | diff --git a/Flow/soc/swerv.config b/Flow/soc/swerv.config index 84f356b..20664f4 100755 --- a/Flow/soc/swerv.config +++ b/Flow/soc/swerv.config @@ -40,7 +40,7 @@ my @asm_vars = qw (xlen reset_vec nmi_vec target dccm.* iccm.* pic.* memmap tes my @asm_overridable = qw (reset_vec nmi_vec serialio external_data) ; # Include these macros in PD (pattern matched) -my @pd_vars = qw (physical retstack target btb.* bht.* dccm.* iccm.* icache.* pic.* bus.* reset_vec nmi_vec build_ahb_lite datawidth ); +my @pd_vars = qw (physical retstack target btb.* bht.* dccm.* iccm.* icache.* pic.* bus.* reset_vec nmi_vec datawidth ); # Dump non-derived/settable vars/values for these vars in stdout : my @dvars = qw(retstack btb bht core dccm iccm icache pic protection memmap bus); @@ -48,7 +48,7 @@ my @dvars = qw(retstack btb bht core dccm iccm icache pic protection memmap bus) # Prefix all macros with my $prefix = "RV_"; # No prefix if keyword has -my $no_prefix = 'RV|tec_rv_icg|regwidth|clock_period|^datawidth|verilator|SDVT_AHB'; +my $no_prefix = 'RV|tec_rv_icg|regwidth|clock_period|^datawidth|verilator'; my $vlog_use__wh = 1; @@ -81,7 +81,7 @@ This script can be run stand-alone by processes not running vsim User options: - -target = {default, default_ahb, high_perf, typical_pd} + -target = {default, high_perf, typical_pd} use default settings for one of the targets -set=var=value @@ -258,8 +258,6 @@ my $icache_tag_num_bypass_width; my $fast_interrupt_redirect = 1; # ON by default my $lsu_num_nbload=4; -my $ahb = 0; -my $axi = 1; my $text_in_iccm = 0; my $lsu2dma = 0; @@ -419,13 +417,8 @@ elsif ($target eq "high_perf") { $btb_size=512; $bht_size=2048; } -elsif ($target eq "default_ahb") { - print "$self: Using target \"default_ahb\"\n"; - $axi = 0; - $ahb = 1; -} else { - die "$self: ERROR! Unsupported target \"$target\". Supported are 'default', 'default_ahb', 'typical_pd', 'high_perf', 'lsu2dma_axi\n" ; + die "$self: ERROR! Unsupported target \"$target\". Supported are 'default', 'typical_pd', 'high_perf', 'lsu2dma_axi\n" ; } @@ -1007,14 +1000,11 @@ our %config = (#{{{ }, "testbench" => { # Testbench only "clock_period" => "100", - "build_ahb_lite" => "$ahb", - "build_axi4" => "$axi", - "build_axi_native" => "1", "ext_datawidth" => "64", "ext_addrwidth" => "32", "sterr_rollback" => "0", "lderr_rollback" => "1", - "SDVT_AHB" => "$ahb", + "SDVT_AHB" => "0", }, "protection" => { # Design parms, Overridable - static MPU "inst_access_enable0" => "0x0", @@ -1179,9 +1169,6 @@ our %verilog_parms = ( "iccm_only" => '1', "icache_only" => '1', "no_iccm_no_icache" => '1', - "build_axi4" => '1', - "build_ahb_lite" => '1', - "build_axi_native" => '1', "lsu_num_nbload_width" => '3', "lsu_num_nbload" => '5', "ret_stack_size" => '4', @@ -1819,45 +1806,10 @@ if ((hex($config{iccm}{iccm_region}) == hex($config{dccm}{dccm_region})) && (hex die "$self: ERROR! ICCM and DCCM blocks collide (region $config{iccm}{iccm_region}, offset $config{dccm}{dccm_offset})!\n"; } -#printf( "axi4 %s\n",$config{"testbench"}{"build_axi4"}); -#printf( "ahb_lite %s\n",$config{"testbench"}{"build_ahb_lite"}); -#printf( "axi_native %s\n",$config{"testbench"}{"build_axi_native"}); - -if( $target eq "el2_formal_axi" ) { - $config{testbench}{build_axi_native} = 1; - $config{testbench}{build_axi4} = 1; - print( "\$config{testbench}{build_axi_native} = $config{testbench}{build_axi_native} \n" ); - print( "\$config{testbench}{build_axi4 } = $config{testbench}{build_axi4 } \n" ); -} - - -if (($config{testbench}{build_ahb_lite} == 1)) { - delete $config{testbench}{build_axi4}; - $config{testbench}{build_axi_native}=1; - $verilog_parms{build_axi4} = 0; -} -elsif (($config{testbench}{build_axi4} == 1)) { - $config{testbench}{build_axi_native}=1; - delete $config{testbench}{build_ahb_lite}; - $verilog_parms{build_ahb_lite} = 0; -} -elsif (($config{testbench}{build_axi_native} == 1)) { - die("illegal to set build_axi_native w/out build_axi4"); -} - -#printf( "axi4 %s\n",$config{"testbench"}{"build_axi4"}); -#printf( "ahb_lite %s\n",$config{"testbench"}{"build_ahb_lite"}); -#printf( "axi_native %s\n",$config{"testbench"}{"build_axi_native"}); - - # Over-ride MFDC reset value for AXI. # Disable Bus barrier and 64b for AXI -if (defined($config{"testbench"}{"build_axi_native"}) && ($config{"testbench"}{"build_axi_native"} ne "0")) { - if (! (defined($config{testbench}{build_ahb_lite}) && $config{testbench}{build_ahb_lite} ne "0")) { - $config{csr}{mfdc}{reset} = "0x00070040" if exists $config{csr}{mfdc}; - } +$config{csr}{mfdc}{reset} = "0x00070040" if exists $config{csr}{mfdc}; -} # parm processing before any values are deleted from the hash @@ -1899,30 +1851,8 @@ $c=$config{btb}{btb_fullya}; if ($c==0 && !grep(/btb_fullya=1/, @sets)) -if ($target eq "default") { -} -elsif (($config{"testbench"}{"build_axi4"} == 1)) { - delete $config{"testbench"}{"build_ahb_lite"}; - delete $config{"testbench"}{"build_axi_native_ahb"}; -} -elsif (($config{"testbench"}{"build_ahb_lite"} == 1)) { - delete $config{"testbench"}{"build_axi4"}; - delete $config{"testbench"}{"build_axi_native"}; - delete $config{"testbench"}{"build_axi_native_ahb"}; -} -elsif (($config{"testbench"}{"build_axi_native_ahb"} == 1)) { - delete $config{"testbench"}{"build_axi4"}; - delete $config{"testbench"}{"build_axi_native_ahb"}; -} -elsif (($config{"testbench"}{"build_axi_native"} == 1)) { - die("illegal to set build_axi_native w/out build_axi4"); -} -else { - delete $config{"testbench"}{"build_ahb_lite"}; - delete $config{"testbench"}{"build_axi4"}; - delete $config{"testbench"}{"build_axi_native"}; - delete $config{"testbench"}{"build_axi_native_ahb"}; -} + +