diff --git a/VexRiscv/murax/main.cpp b/VexRiscv/murax/main.cpp index 735875f..41a4a33 100644 --- a/VexRiscv/murax/main.cpp +++ b/VexRiscv/murax/main.cpp @@ -1,13 +1,13 @@ -#include "VMurax.h" -#include "VMurax_Murax.h" +#include "Vsoc.h" +#include "Vsoc_soc.h" #include "verilated.h" #include "verilated_vcd_c.h" #include "../common/framework.h" -#include "../common/jtag.h" +// #include "../common/jtag.h" #include "../common/uart.h" -class MuraxWorkspace : public Workspace{ +class MuraxWorkspace : public Workspace{ public: MuraxWorkspace() : Workspace("Murax"){ ClockDomain *mainClk = new ClockDomain(&top->io_mainClk,NULL,83333,300000); @@ -20,8 +20,8 @@ public: timeProcesses.push_back(uartRx); timeProcesses.push_back(uartTx); - Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,83333*4); - timeProcesses.push_back(jtag); + // Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,83333*4); + // timeProcesses.push_back(jtag); #ifdef TRACE //speedFactor = 10e-3; diff --git a/VexRiscv/murax/makefile b/VexRiscv/murax/makefile index 004d126..e140011 100644 --- a/VexRiscv/murax/makefile +++ b/VexRiscv/murax/makefile @@ -21,18 +21,20 @@ endif ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START} - +FILELIST = -F ./dpi/jtag.fl all: clean compile run: compile - ./obj_dir/VMurax + ./obj_dir/Vsoc -verilate: ./Murax.v - verilator -cc ./Murax.v ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp +verilate: ./soc.v + verilator -cc ./soc.v ./Murax.v ${FILELIST} ${ADDCFLAGS} \ + -Wno-WIDTH -Wno-UNOPTFLAT -Wno-TIMESCALEMOD \ + --x-assign unique --exe main.cpp --gdbbt ${VERILATOR_ARGS} compile: verilate - make -j -C obj_dir/ -f VMurax.mk VMurax + make -j -C obj_dir/ -f Vsoc.mk Vsoc clean: rm -rf obj_dir diff --git a/VexRiscv/murax/soc.v b/VexRiscv/murax/soc.v new file mode 100644 index 0000000..c7d2fee --- /dev/null +++ b/VexRiscv/murax/soc.v @@ -0,0 +1,58 @@ + +`timescale 1ns/1ps + + +module soc ( + input wire io_asyncReset, + input wire io_mainClk, + input wire [31:0] io_gpioA_read, + output wire [31:0] io_gpioA_write, + output wire [31:0] io_gpioA_writeEnable, + output wire io_uart_txd, + input wire io_uart_rxd +); + +wire jtag_tck; +wire jtag_tms; +wire jtag_tdi; +wire jtag_tdo; + +bit [31:0] cycleCnt; +always @(posedge io_mainClk) begin + cycleCnt <= cycleCnt + 1; +end + +wire clk; +assign clk = cycleCnt[2]; +logic rst_l; +assign rst_l = cycleCnt > 100; + +Murax murax( + .io_asyncReset(io_asyncReset), + .io_mainClk(io_mainClk), + + .io_jtag_tms(jtag_tms), + .io_jtag_tdi(jtag_tdi), + .io_jtag_tdo(jtag_tdo), + .io_jtag_tck(jtag_tck), + + .io_gpioA_read(io_gpioA_read), + .io_gpioA_write(io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(io_uart_txd), + .io_uart_rxd(io_uart_rxd) +); + +jtagdpi jtagdpi ( + .clk_i (io_mainClk), + .rst_ni(rst_l), + + .jtag_tck(jtag_tck), + .jtag_tms(jtag_tms), + .jtag_tdi(jtag_tdi), + .jtag_tdo(jtag_tdo), + .jtag_trst_n(), + .jtag_srst_n() +); + +endmodule \ No newline at end of file diff --git a/VexRiscv/sim/Makefile b/VexRiscv/sim/Makefile index b4d9b36..44f7833 100644 --- a/VexRiscv/sim/Makefile +++ b/VexRiscv/sim/Makefile @@ -44,7 +44,9 @@ verilator: verilator-build ##################### openocd ##################################### openocd: - openocd -f jtag_tcp.cfg -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg + # openocd -f jtag_tcp.cfg -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg + # openocd -c "set MURAX_CPU0_YAML cpu0.yaml" -f murax.cfg + openocd -f murax.cfg gdb: $(GDB_PREFIX) -x gdbinit ./hello_world.elf diff --git a/VexRiscv/sim/murax.cfg b/VexRiscv/sim/murax.cfg index a842685..7c47c95 100644 --- a/VexRiscv/sim/murax.cfg +++ b/VexRiscv/sim/murax.cfg @@ -1,30 +1,54 @@ -transport select jtag -set _ENDIAN little -set _TAP_TYPE 1234 + + +adapter driver remote_bitbang +remote_bitbang host localhost +remote_bitbang port 44853 + + +# transport select jtag + + +# set _ENDIAN little +# set _TAP_TYPE 1234 if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # set useful default - set _CPUTAPID 0x10001fff + set _CPUTAPID 0x10001fff } -adapter_khz 800 -adapter_nsrst_delay 260 -jtag_ntrst_delay 250 +# adapter_khz 800 +# adapter_nsrst_delay 260 +# jtag_ntrst_delay 250 -set _CHIPNAME fpga_spinal -jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0xF +set _CHIPNAME murax +set _TARGETNAME $_CHIPNAME.tap -target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge -coreid 0 -dbgbase 0xF00F0000 -vexriscv readWaitCycles 12 -vexriscv cpuConfigFile $MURAX_CPU0_YAML +jtag newtap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -poll_period 50 +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +# vexriscv readWaitCycles 12 +# vexriscv cpuConfigFile $MURAX_CPU0_YAML + +# Be verbose about GDB errors +gdb_report_data_abort enable +gdb_report_register_access_error enable + + +#poll_period 50 + +# Conclude OpenOCD configuration init -#echo "Halting processor" -soft_reset_halt -sleep 1000 + +# Halt the target +halt + + +# init +# #echo "Halting processor" +# soft_reset_halt +# sleep 1000 diff --git a/VexRiscv/sim/riscv.cfg b/VexRiscv/sim/riscv.cfg new file mode 100644 index 0000000..4abd3b7 --- /dev/null +++ b/VexRiscv/sim/riscv.cfg @@ -0,0 +1,39 @@ +# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket +# speaking the remote_bitbang protocol. The adapter is implemented as +# SystemVerilog DPI module. + + +# reset_config srst_only # donot support TRST, use five tms=1 +# adapter_nsrst_assert_width 100 + +adapter driver remote_bitbang +remote_bitbang host localhost +remote_bitbang port 44853 + +# Target configuration for the riscv chip + +set _CHIPNAME riscv +set _TARGETNAME $_CHIPNAME.tap + +jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x10000B6F +# {4'h1, 16'h0, 12'b1011_011_0111_1}; + +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +# Configure work area in on-chip SRAM +# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0 + +riscv expose_csrs 1988 + +# Be verbose about GDB errors +gdb_report_data_abort enable +gdb_report_register_access_error enable + +# Increase timeouts in simulation +riscv set_command_timeout_sec 1200 + +# Conclude OpenOCD configuration +init + +# Halt the target +halt