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--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
-# SweRV RISC-V CoreTM 1.4 from Western Digital
+# SweRV RISC-V CoreTM 1.5 from Western Digital
-This repository contains the SweRV CoreTM 1.3 design RTL. The previous version can be found in [branch 1.3.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.3)
+This repository contains the SweRV CoreTM 1.5 design RTL. The previous version can be found in [branch 1.4.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.4)
The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M).
## License