From a44ef01adf94b8de102eb21de93d0019ef747554 Mon Sep 17 00:00:00 2001 From: Joseph Rahmeh Date: Tue, 18 Feb 2020 13:41:42 -0800 Subject: [PATCH] Changed version to 1.5. --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 2b002ba..9671a03 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ -# SweRV RISC-V CoreTM 1.4 from Western Digital +# SweRV RISC-V CoreTM 1.5 from Western Digital -This repository contains the SweRV CoreTM 1.3 design RTL. The previous version can be found in [branch 1.3.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.3) +This repository contains the SweRV CoreTM 1.5 design RTL. The previous version can be found in [branch 1.4.](https://github.com/chipsalliance/Cores-SweRV/tree/branch1.4) The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M). ## License