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Fixed FPGA build error

This commit is contained in:
Arup De 2019-12-06 09:50:38 -08:00
parent c89f6b7511
commit aa2bc2269d
1 changed files with 2 additions and 2 deletions
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4
design/dmi/dmi_jtag_to_core_sync.v
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@ -48,8 +48,8 @@ module dmi_jtag_to_core_sync (
// synchronizers // synchronizers
always @ ( posedge clk or negedge rst_n) begin always @ ( posedge clk or negedge rst_n) begin
if(!rst_n) begin if(!rst_n) begin
rden <= '0; rden <= 3'b0;
wren <= '0; wren <= 3'b0;
end end
else begin else begin
rden <= {rden[1:0], rd_en}; rden <= {rden[1:0], rd_en};