Fixed FPGA build error

design/dmi/dmi_jtag_to_core_sync.v

@@ -48,8 +48,8 @@ module dmi_jtag_to_core_sync (
 // synchronizers  
 always @ ( posedge clk or negedge rst_n) begin
     if(!rst_n) begin
-        rden <= '0;
-        wren <= '0;
+        rden <= 3'b0;
+        wren <= 3'b0;
     end
     else begin
         rden <= {rden[1:0], rd_en};