add quasar fpga.

This commit is contained in:
colin 2022-03-09 11:16:13 +00:00
parent 33885bbccb
commit beab126fc5
5 changed files with 113 additions and 2 deletions

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gen/

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LOCATE COMP "clk" SITE "P3";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk" 25 MHZ;
LOCATE COMP "dbg_rst" SITE "N2";
IOBUF PORT "dbg_rst" IO_TYPE=LVCMOS33;
FREQUENCY PORT "dbg_rst" 25 MHZ;
LOCATE COMP "rst" SITE "N3";
IOBUF PORT "rst" IO_TYPE=LVCMOS33;
FREQUENCY PORT "rst" 25 MHZ;
LOCATE COMP "jtag_tck" SITE "T2";
IOBUF PORT "jtag_tck" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tck" 25 MHZ;
LOCATE COMP "jtag_tms" SITE "T3";
IOBUF PORT "jtag_tms" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tms" 25 MHZ;
LOCATE COMP "jtag_tdi" SITE "N4";
IOBUF PORT "jtag_tdi" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tdi" 25 MHZ;
LOCATE COMP "jtag_trst_n" SITE "M3";
IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_trst_n" 25 MHZ;
LOCATE COMP "jtag_tdo" SITE "M4";
IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;

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#!/bin/bash
# if [ $# -ne 1 -o ! -d "$1" ]; then
# echo "Usage: $0 <design>" >&2
# exit 1
# fi
set -ex
PWD=$(pwd)
SOC=$PWD/../../quasar
design=${1%/}
YOSYS_COARSE=true
YOSYS_GLOBRST=false
YOSYS_SPLITNETS=false
TOP="soc_top"
RTL=$(cat ../../quasar/soc_top.mk)
rtl_files=""
for src in $RTL; do
rtl_files="$rtl_files $SOC/$src"
done
mkdir -p gen
rm -rf gen/*
mkdir gen/design
BUILD_PATH=gen/ PERLLIB=${SOC} ${SOC}/swerv.config -target=default -set iccm_enable
filelist=""
for file in $rtl_files; do
filelist="$filelist $file"
done
sv2v -Igen -I/home/colin/develop/AbstractAccelerator/Cores-SweRV/design/include \
gen/common_defines.vh $filelist > gen/soc_top.v
{
# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
# for file in $rtl_files; do
# echo "read_verilog -sv -I../../design/include $file"
# done
echo "read_verilog gen/soc_top.v"
if test -n "$TOP"; then
echo "hierarchy -check -top $TOP"
else
echo "hierarchy -check"
fi
if $YOSYS_GLOBRST; then
# insertation of global reset (e.g. for FPGA cores)
echo "add -global_input globrst 1"
echo "proc -global_arst globrst"
fi
echo "synth -run coarse; opt -fine"
# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
if ! $YOSYS_COARSE; then
echo "memory_map; techmap; opt; abc -dff; clean"
fi
if $YOSYS_SPLITNETS; then
# icarus verilog has a performance problems when there are
# dependencies between the bits of a long vector
echo "splitnets; clean"
fi
if $YOSYS_COARSE; then
echo "write_verilog -noexpr -noattr gen/synth.v"
else
echo "select -assert-none t:\$[!_]"
echo "write_verilog -noattr gen/synth.v"
fi
echo "synth_ecp5 -top $TOP -json gen/soc.json"
# echo "synth_xilinx -top $TOP"
} > gen/synth.ys
yosys -v2 -l gen/synth.log gen/synth.ys
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1 --json gen/soc.json

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# set debug remote 1
target remote :3333 target remote :3333
set remotetimeout 2000 set remotetimeout 2000

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@ -8,8 +8,8 @@ vsrc/dmi_wrapper.sv
vsrc/dmi_jtag_to_core_sync.sv vsrc/dmi_jtag_to_core_sync.sv
vsrc/rvjtag_tap.sv vsrc/rvjtag_tap.sv
vsrc/gated_latch.sv vsrc/gated_latch.sv
-v vsrc/beh_lib.sv vsrc/beh_lib.sv
-v vsrc/mem_lib.sv vsrc/mem_lib.sv
./ahb_sif.sv ./ahb_sif.sv
./axi_lsu_dma_bridge.sv ./axi_lsu_dma_bridge.sv