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Add ivlpp to gen single file of RTL.

This commit is contained in:
colin.liang 2023-01-05 21:28:53 +08:00
parent 44161e293f
commit c57450fa1c
5 changed files with 3819 additions and 6 deletions
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9
uriscv/demo/Makefile
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@ -32,15 +32,14 @@ clean:
rm -rf build obj_dir rm -rf build obj_dir
##################### Verilog Builds ##################################### ##################### Verilog Builds #####################################
top.v:
./ivlpp -F include.f -f soc.mk -o top.v
verilator-build: verilator-build: top.v
verilator --cc -CFLAGS ${CFLAGS} \ verilator --cc -CFLAGS ${CFLAGS} \
-Wno-WIDTH \ -Wno-WIDTH \
-Wno-UNOPTFLAT \ -Wno-UNOPTFLAT \
-Wno-LATCH \ top.v \
-I../src \
-F ./soc.mk \
soc_sim.v \
--top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG) --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
cp ${DEMODIR}/test_soc_sim.cpp obj_dir cp ${DEMODIR}/test_soc_sim.cpp obj_dir
$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS) $(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)

1
uriscv/demo/include.f Normal file
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@ -0,0 +1 @@
I:../src/

BIN
uriscv/demo/ivlpp Executable file
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3
uriscv/demo/soc.mk
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@ -8,4 +8,5 @@
./soc_top.v ./soc_top.v
./tcm_mem_ram.v ./tcm_mem_ram.v
./tcm_mem.v ./tcm_mem.v
./soc_sim.v

3812
uriscv/demo/top.v Normal file
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