Add ivlpp to gen single file of RTL.

uriscv/demo/Makefile

@@ -32,15 +32,14 @@ clean:
 	rm -rf build obj_dir
 
 ##################### Verilog Builds #####################################
+top.v:
+	./ivlpp -F include.f -f soc.mk -o top.v
 
-verilator-build:
+verilator-build: top.v
 	verilator --cc -CFLAGS ${CFLAGS} \
 								-Wno-WIDTH \
 	              -Wno-UNOPTFLAT \
-								-Wno-LATCH \
-								-I../src \
-	              -F ./soc.mk \
-	              soc_sim.v \
+	              top.v \
 	              --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
 	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
 	$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)

uriscv/demo/include.f

@@ -0,0 +1 @@
+I:../src/

uriscv/demo/soc.mk

@@ -8,4 +8,5 @@
 
 ./soc_top.v
 ./tcm_mem_ram.v
-./tcm_mem.v
+./tcm_mem.v
+./soc_sim.v