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Fixed release notes

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jrahmeh 2019-08-13 15:08:45 -05:00 committed by GitHub
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release-notes.md
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@ -3,8 +3,8 @@
1. SWERV core RISCV compatibility improvements 1. SWERV core RISCV compatibility improvements
* The ebreak and ecall instructions are no longer counted in the MINSRET * The ebreak and ecall instructions are no longer counted in the MINSRET
control and status register. control and status register.
* Write to SBDATA0 does not start an SB write access when * Write to SBDATA0 does not start SB write access when both
sbreadonaddr/dbreadondata is set. sbreadonaddr/sbreadondata are zero.
1. FPGA support: Add fpga_optimize option to swerv.config which 1. FPGA support: Add fpga_optimize option to swerv.config which
eliminates over 90% of clock-gating enabling faster FPGA eliminates over 90% of clock-gating enabling faster FPGA