Fixed release notes
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@ -3,8 +3,8 @@
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1. SWERV core RISCV compatibility improvements
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* The ebreak and ecall instructions are no longer counted in the MINSRET
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control and status register.
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* Write to SBDATA0 does not start an SB write access when
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sbreadonaddr/dbreadondata is set.
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* Write to SBDATA0 does not start SB write access when both
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sbreadonaddr/sbreadondata are zero.
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1. FPGA support: Add fpga_optimize option to swerv.config which
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eliminates over 90% of clock-gating enabling faster FPGA
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