From cffec82632b15cfc55ae92c94b45389de38df468 Mon Sep 17 00:00:00 2001
From: colin <lianghongkey@gmail.com>
Date: Thu, 17 Feb 2022 06:20:57 +0000
Subject: [PATCH] Add clean before fpga ram make all

---
 fpga/ram/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/ram/Makefile b/fpga/ram/Makefile
index e584004..40fa4a3 100644
--- a/fpga/ram/Makefile
+++ b/fpga/ram/Makefile
@@ -3,7 +3,7 @@ TARGET=top
 OBJS+=top.sv
 OBJS+=bram.sv
 
-all: ${TARGET}.bit
+all: clean ${TARGET}.bit
 
 $(TARGET).json: $(OBJS)
 	yosys -p "read_verilog -sv $(OBJS); synth_ecp5 -top ${TARGET} -json $@"