diff --git a/uriscv/README.md b/uriscv/README.md
index a311cbb..268e65d 100644
--- a/uriscv/README.md
+++ b/uriscv/README.md
@@ -22,15 +22,6 @@ Most instructions take 2 cycles, apart from load/stores which take 4+ cycles (de
 
 ## Getting Started
 
-#### Cloning
-
-To clone this project and its dependencies;
-
-```
-git clone https://github.com/ultraembedded/core_uriscv.git
-
-```
-
 #### Running Helloworld
 
 To run a simple test image on the core RTL using Icarus Verilog;
@@ -43,7 +34,7 @@ sudo apt-get install iverilog
 #sudo yum install iverilog
 
 # Run a simple test image (test.elf)
-cd tb/tb_core_icarus
+cd demo
 make
 ```