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Riviera simulator added to Readme

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Daniel Mlynek 2020-02-27 09:40:53 +01:00
parent 0dbee1c24c
commit e1aec7d193
1 changed files with 3 additions and 3 deletions
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README.md
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@ -142,9 +142,9 @@ make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=<snapshot>] [t
where: where:
<simulator> - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa <simulator> - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa,
if not provided, 'make' cleans work directory, builds verilator executable and runs a test. 'riviera' - Aldec Riviera-PRO if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option. debug=1 - allows VCD generation for verilator, VCS and Riviera-PRO and SHM waves for irun option.
<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'default_pd', 'high_perf' <target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'default_pd', 'high_perf'
TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default
TEST_DIR - alternative to test source directory testbench/asm TEST_DIR - alternative to test source directory testbench/asm