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Delete rvdff by fpga.

This commit is contained in:
colin 2022-05-23 15:37:09 +00:00
parent a8c8d46382
commit e23aca0cfc
6 changed files with 65 additions and 314 deletions
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44
Flow/design/el2_dma_ctrl.sv
View File

@ -534,20 +534,16 @@ module el2_dma_ctrl #(
); );
// Inputs // Inputs
rvdff_fpga #(1) fifo_full_bus_ff ( rvdff #(1) fifo_full_bus_ff (
.din(fifo_full_spec), .din(fifo_full_spec),
.dout(fifo_full_spec_bus), .dout(fifo_full_spec_bus),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdff_fpga #(1) dbg_dma_bubble_ff ( rvdff #(1) dbg_dma_bubble_ff (
.din(dbg_dma_bubble), .din(dbg_dma_bubble),
.dout(dbg_dma_bubble_bus), .dout(dbg_dma_bubble_bus),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdff #(1) dma_dbg_cmd_doneff ( rvdff #(1) dma_dbg_cmd_doneff (
@ -585,7 +581,7 @@ module el2_dma_ctrl #(
assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en; assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en;
assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en; assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en;
rvdffsc_fpga #( rvdffsc #(
.WIDTH(1) .WIDTH(1)
) wrbuf_vldff ( ) wrbuf_vldff (
.din(1'b1), .din(1'b1),
@ -593,11 +589,9 @@ module el2_dma_ctrl #(
.en(wrbuf_en), .en(wrbuf_en),
.clear(wrbuf_rst), .clear(wrbuf_rst),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdffsc_fpga #( rvdffsc #(
.WIDTH(1) .WIDTH(1)
) wrbuf_data_vldff ( ) wrbuf_data_vldff (
.din(1'b1), .din(1'b1),
@ -605,30 +599,24 @@ module el2_dma_ctrl #(
.en(wrbuf_data_en), .en(wrbuf_data_en),
.clear(wrbuf_data_rst), .clear(wrbuf_data_rst),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(pt.DMA_BUS_TAG) .WIDTH(pt.DMA_BUS_TAG)
) wrbuf_tagff ( ) wrbuf_tagff (
.din(dma_axi_awid[pt.DMA_BUS_TAG-1:0]), .din(dma_axi_awid[pt.DMA_BUS_TAG-1:0]),
.dout(wrbuf_tag[pt.DMA_BUS_TAG-1:0]), .dout(wrbuf_tag[pt.DMA_BUS_TAG-1:0]),
.en(wrbuf_en), .en(wrbuf_en),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(3) .WIDTH(3)
) wrbuf_szff ( ) wrbuf_szff (
.din(dma_axi_awsize[2:0]), .din(dma_axi_awsize[2:0]),
.dout(wrbuf_sz[2:0]), .dout(wrbuf_sz[2:0]),
.en(wrbuf_en), .en(wrbuf_en),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdffe #( rvdffe #(
@ -647,15 +635,13 @@ module el2_dma_ctrl #(
.en (wrbuf_data_en & dma_bus_clk_en), .en (wrbuf_data_en & dma_bus_clk_en),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(8) .WIDTH(8)
) wrbuf_byteenff ( ) wrbuf_byteenff (
.din(dma_axi_wstrb[7:0]), .din(dma_axi_wstrb[7:0]),
.dout(wrbuf_byteen[7:0]), .dout(wrbuf_byteen[7:0]),
.en(wrbuf_data_en), .en(wrbuf_data_en),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
@ -664,7 +650,7 @@ module el2_dma_ctrl #(
assign rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write; assign rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write;
assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en; assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en;
rvdffsc_fpga #( rvdffsc #(
.WIDTH(1) .WIDTH(1)
) rdbuf_vldff ( ) rdbuf_vldff (
.din(1'b1), .din(1'b1),
@ -672,30 +658,24 @@ module el2_dma_ctrl #(
.en(rdbuf_en), .en(rdbuf_en),
.clear(rdbuf_rst), .clear(rdbuf_rst),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(pt.DMA_BUS_TAG) .WIDTH(pt.DMA_BUS_TAG)
) rdbuf_tagff ( ) rdbuf_tagff (
.din(dma_axi_arid[pt.DMA_BUS_TAG-1:0]), .din(dma_axi_arid[pt.DMA_BUS_TAG-1:0]),
.dout(rdbuf_tag[pt.DMA_BUS_TAG-1:0]), .dout(rdbuf_tag[pt.DMA_BUS_TAG-1:0]),
.en(rdbuf_en), .en(rdbuf_en),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(3) .WIDTH(3)
) rdbuf_szff ( ) rdbuf_szff (
.din(dma_axi_arsize[2:0]), .din(dma_axi_arsize[2:0]),
.dout(rdbuf_sz[2:0]), .dout(rdbuf_sz[2:0]),
.en(rdbuf_en), .en(rdbuf_en),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );
rvdffe #( rvdffe #(
@ -728,15 +708,13 @@ module el2_dma_ctrl #(
assign axi_mstr_sel = (wrbuf_vld & wrbuf_data_vld & rdbuf_vld) ? axi_mstr_priority : (wrbuf_vld & wrbuf_data_vld); assign axi_mstr_sel = (wrbuf_vld & wrbuf_data_vld & rdbuf_vld) ? axi_mstr_priority : (wrbuf_vld & wrbuf_data_vld);
assign axi_mstr_prty_in = ~axi_mstr_priority; assign axi_mstr_prty_in = ~axi_mstr_priority;
assign axi_mstr_prty_en = bus_cmd_sent; assign axi_mstr_prty_en = bus_cmd_sent;
rvdffs_fpga #( rvdffs #(
.WIDTH(1) .WIDTH(1)
) mstr_prtyff ( ) mstr_prtyff (
.din(axi_mstr_prty_in), .din(axi_mstr_prty_in),
.dout(axi_mstr_priority), .dout(axi_mstr_priority),
.en(axi_mstr_prty_en), .en(axi_mstr_prty_en),
.clk(dma_bus_clk), .clk(dma_bus_clk),
.clken(dma_bus_clk_en),
.rawclk(clk),
.* .*
); );

33
Flow/design/el2_pic_ctrl.sv
View File

@ -345,32 +345,6 @@ end
assign intenable_clk_enable[i] = gw_config_reg[i][1] | intenable_reg_we[i] | intenable_reg[i] | gw_clear_reg_we[i] ; assign intenable_clk_enable[i] = gw_config_reg[i][1] | intenable_reg_we[i] | intenable_reg[i] | gw_clear_reg_we[i] ;
/*
rvsyncss_fpga #(1) sync_inst
(
.gw_clk (gw_clk[i/4]),
.rawclk (clk),
.clken (intenable_clk_enable_grp[i/4]),
.dout (extintsrc_req_sync[i]),
.din (extintsrc_req[i]),
.*) ;
el2_configurable_gw config_gw_inst(.*,
.gw_clk(gw_clk[i/4]),
.rawclk(clk),
.clken (intenable_clk_enable_grp[i/4]),
.extintsrc_req_sync(extintsrc_req_sync[i]) ,
.meigwctrl_polarity(gw_config_reg[i][0]) ,
.meigwctrl_type(gw_config_reg[i][1]) ,
.meigwclr(gw_clear_reg_we[i]) ,
.extintsrc_req_config(extintsrc_req_gw[i])
);
*/
end else begin : INT_ZERO end else begin : INT_ZERO
assign intpriority_reg_we[i] = 1'b0 ; assign intpriority_reg_we[i] = 1'b0 ;
assign intpriority_reg_re[i] = 1'b0 ; assign intpriority_reg_re[i] = 1'b0 ;
@ -700,7 +674,8 @@ module el2_configurable_gw (
logic gw_int_pending_in, gw_int_pending, extintsrc_req_sync; logic gw_int_pending_in, gw_int_pending, extintsrc_req_sync;
rvsyncss_fpga #(1) sync_inst ( rvsyncss #(1) sync_inst (
.clk (gw_clk),
.dout(extintsrc_req_sync), .dout(extintsrc_req_sync),
.din (extintsrc_req), .din (extintsrc_req),
.* .*
@ -708,11 +683,9 @@ module el2_configurable_gw (
assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr) ; assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr) ;
rvdff_fpga #(1) int_pend_ff ( rvdff #(1) int_pend_ff (
.*, .*,
.clk (gw_clk), .clk (gw_clk),
.rawclk(rawclk),
.clken(clken),
.din (gw_int_pending_in), .din (gw_int_pending_in),
.dout(gw_int_pending) .dout(gw_int_pending)
); );

4
Flow/design/ifu/el2_ifu_bp_ctl.sv
View File

@ -980,12 +980,10 @@ pt.BTB_SIZE
rvdffs_fpga #(2) bht_bank ( rvdffs #(2) bht_bank (
.*, .*,
.clk (bht_bank_clk[i][k]), .clk (bht_bank_clk[i][k]),
.en (bank_sel), .en (bank_sel),
.rawclk(clk),
.clken (bank_sel),
.din (wdata), .din (wdata),
.dout (bht_bank_rd_data_out[i][(16*k)+j]) .dout (bht_bank_rd_data_out[i][(16*k)+j])
); );

80
Flow/design/ifu/el2_ifu_mem_ctl.sv
View File

@ -592,11 +592,9 @@ module el2_ifu_mem_ctl
assign uncacheable_miss_scnd_in = sel_hold_imb_scnd ? uncacheable_miss_scnd_ff : ifc_fetch_uncacheable_bf ; assign uncacheable_miss_scnd_in = sel_hold_imb_scnd ? uncacheable_miss_scnd_ff : ifc_fetch_uncacheable_bf ;
rvdff_fpga #(1) unc_miss_scnd_ff ( rvdff #(1) unc_miss_scnd_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din(uncacheable_miss_scnd_in), .din(uncacheable_miss_scnd_in),
.dout(uncacheable_miss_scnd_ff) .dout(uncacheable_miss_scnd_ff)
); );
@ -606,19 +604,15 @@ module el2_ifu_mem_ctl
.din ({imb_scnd_in[31:1]}), .din ({imb_scnd_in[31:1]}),
.dout({imb_scnd_ff[31:1]}) .dout({imb_scnd_ff[31:1]})
); );
rvdff_fpga #(pt.ICACHE_STATUS_BITS) mb_rep_wayf2_scnd_ff ( rvdff #(pt.ICACHE_STATUS_BITS) mb_rep_wayf2_scnd_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din({way_status_mb_scnd_in[pt.ICACHE_STATUS_BITS-1:0]}), .din({way_status_mb_scnd_in[pt.ICACHE_STATUS_BITS-1:0]}),
.dout({way_status_mb_scnd_ff[pt.ICACHE_STATUS_BITS-1:0]}) .dout({way_status_mb_scnd_ff[pt.ICACHE_STATUS_BITS-1:0]})
); );
rvdff_fpga #(pt.ICACHE_NUM_WAYS) mb_tagv_scnd_ff ( rvdff #(pt.ICACHE_NUM_WAYS) mb_tagv_scnd_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din({tagv_mb_scnd_in[pt.ICACHE_NUM_WAYS-1:0]}), .din({tagv_mb_scnd_in[pt.ICACHE_NUM_WAYS-1:0]}),
.dout({tagv_mb_scnd_ff[pt.ICACHE_NUM_WAYS-1:0]}) .dout({tagv_mb_scnd_ff[pt.ICACHE_NUM_WAYS-1:0]})
); );
@ -678,11 +672,9 @@ module el2_ifu_mem_ctl
.din (imb_in[31:1]), .din (imb_in[31:1]),
.dout(imb_ff[31:1]) .dout(imb_ff[31:1])
); );
rvdff_fpga #(1) unc_miss_ff ( rvdff #(1) unc_miss_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din(uncacheable_miss_in), .din(uncacheable_miss_in),
.dout(uncacheable_miss_ff) .dout(uncacheable_miss_ff)
); );
@ -706,19 +698,15 @@ module el2_ifu_mem_ctl
rvdff_fpga #(pt.ICACHE_STATUS_BITS) mb_rep_wayf2_ff ( rvdff #(pt.ICACHE_STATUS_BITS) mb_rep_wayf2_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din({way_status_mb_in[pt.ICACHE_STATUS_BITS-1:0]}), .din({way_status_mb_in[pt.ICACHE_STATUS_BITS-1:0]}),
.dout({way_status_mb_ff[pt.ICACHE_STATUS_BITS-1:0]}) .dout({way_status_mb_ff[pt.ICACHE_STATUS_BITS-1:0]})
); );
rvdff_fpga #(pt.ICACHE_NUM_WAYS) mb_tagv_ff ( rvdff #(pt.ICACHE_NUM_WAYS) mb_tagv_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din({tagv_mb_in[pt.ICACHE_NUM_WAYS-1:0]}), .din({tagv_mb_in[pt.ICACHE_NUM_WAYS-1:0]}),
.dout({tagv_mb_ff[pt.ICACHE_NUM_WAYS-1:0]}) .dout({tagv_mb_ff[pt.ICACHE_NUM_WAYS-1:0]})
); );
@ -727,27 +715,21 @@ module el2_ifu_mem_ctl
assign ifc_fetch_req_f = ifc_fetch_req_f_raw & ~exu_flush_final; assign ifc_fetch_req_f = ifc_fetch_req_f_raw & ~exu_flush_final;
rvdff_fpga #(1) ifu_iccm_acc_ff ( rvdff #(1) ifu_iccm_acc_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din(ifc_iccm_access_bf), .din(ifc_iccm_access_bf),
.dout(ifc_iccm_access_f) .dout(ifc_iccm_access_f)
); );
rvdff_fpga #(1) ifu_iccm_reg_acc_ff ( rvdff #(1) ifu_iccm_reg_acc_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din(ifc_region_acc_fault_final_bf), .din(ifc_region_acc_fault_final_bf),
.dout(ifc_region_acc_fault_final_f) .dout(ifc_region_acc_fault_final_f)
); );
rvdff_fpga #(1) rgn_acc_ff ( rvdff #(1) rgn_acc_ff (
.*, .*,
.clk(fetch_bf_f_c1_clk), .clk(fetch_bf_f_c1_clk),
.clken(fetch_bf_f_c1_clken),
.rawclk(clk),
.din(ifc_region_acc_fault_bf), .din(ifc_region_acc_fault_bf),
.dout(ifc_region_acc_fault_f) .dout(ifc_region_acc_fault_f)
); );
@ -1204,11 +1186,9 @@ module el2_ifu_mem_ctl
assign ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & ~dec_tlu_force_halt & ~((bus_cmd_beat_count== {pt.ICACHE_BEAT_BITS{1'b1}}) & ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending); assign ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & ~dec_tlu_force_halt & ~((bus_cmd_beat_count== {pt.ICACHE_BEAT_BITS{1'b1}}) & ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending);
rvdff_fpga #(1) bus_ic_req_ff2 ( rvdff #(1) bus_ic_req_ff2 (
.*, .*,
.clk(busclk_force), .clk(busclk_force),
.clken(bus_ifu_bus_clk_en | dec_tlu_force_halt),
.rawclk(clk),
.din(ifc_bus_ic_req_ff_in), .din(ifc_bus_ic_req_ff_in),
.dout(ifu_bus_cmd_valid) .dout(ifu_bus_cmd_valid)
); );
@ -1256,43 +1236,33 @@ module el2_ifu_mem_ctl
assign ifu_bus_rvalid_unq = ifu_axi_rvalid; assign ifu_bus_rvalid_unq = ifu_axi_rvalid;
assign ifu_bus_arvalid = ifu_axi_arvalid; assign ifu_bus_arvalid = ifu_axi_arvalid;
rvdff_fpga #(1) bus_rdy_ff ( rvdff #(1) bus_rdy_ff (
.*, .*,
.clk(busclk), .clk(busclk),
.clken(bus_ifu_bus_clk_en),
.rawclk(clk),
.din(ifu_bus_arready_unq), .din(ifu_bus_arready_unq),
.dout(ifu_bus_arready_unq_ff) .dout(ifu_bus_arready_unq_ff)
); );
rvdff_fpga #(1) bus_rsp_vld_ff ( rvdff #(1) bus_rsp_vld_ff (
.*, .*,
.clk(busclk), .clk(busclk),
.clken(bus_ifu_bus_clk_en),
.rawclk(clk),
.din(ifu_bus_rvalid_unq), .din(ifu_bus_rvalid_unq),
.dout(ifu_bus_rvalid_unq_ff) .dout(ifu_bus_rvalid_unq_ff)
); );
rvdff_fpga #(1) bus_cmd_ff ( rvdff #(1) bus_cmd_ff (
.*, .*,
.clk(busclk), .clk(busclk),
.clken(bus_ifu_bus_clk_en),
.rawclk(clk),
.din(ifu_bus_arvalid), .din(ifu_bus_arvalid),
.dout(ifu_bus_arvalid_ff) .dout(ifu_bus_arvalid_ff)
); );
rvdff_fpga #(2) bus_rsp_cmd_ff ( rvdff #(2) bus_rsp_cmd_ff (
.*, .*,
.clk(busclk), .clk(busclk),
.clken(bus_ifu_bus_clk_en),
.rawclk(clk),
.din(ifu_axi_rresp[1:0]), .din(ifu_axi_rresp[1:0]),
.dout(ifu_bus_rresp_ff[1:0]) .dout(ifu_bus_rresp_ff[1:0])
); );
rvdff_fpga #(pt.IFU_BUS_TAG) bus_rsp_tag_ff ( rvdff #(pt.IFU_BUS_TAG) bus_rsp_tag_ff (
.*, .*,
.clk(busclk), .clk(busclk),
.clken(bus_ifu_bus_clk_en),
.rawclk(clk),
.din(ifu_axi_rid[pt.IFU_BUS_TAG-1:0]), .din(ifu_axi_rid[pt.IFU_BUS_TAG-1:0]),
.dout(ifu_bus_rid_ff[pt.IFU_BUS_TAG-1:0]) .dout(ifu_bus_rid_ff[pt.IFU_BUS_TAG-1:0])
); );
@ -1349,11 +1319,9 @@ module el2_ifu_mem_ctl
( bus_cmd_sent ) ? (bus_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0] + 3'b001) : ( bus_cmd_sent ) ? (bus_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0] + 3'b001) :
bus_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0]; bus_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0];
rvdff_fpga #(pt.ICACHE_BEAT_BITS) bus_rd_addr_ff ( rvdff #(pt.ICACHE_BEAT_BITS) bus_rd_addr_ff (
.*, .*,
.clk(busclk_reset), .clk(busclk_reset),
.clken(bus_ifu_bus_clk_en | ic_act_miss_f | dec_tlu_force_halt),
.rawclk(clk),
.din({bus_new_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0]}), .din({bus_new_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0]}),
.dout({bus_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0]}) .dout({bus_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0]})
); );
@ -1379,11 +1347,9 @@ module el2_ifu_mem_ctl
.* .*
); );
rvdffs_fpga #(pt.ICACHE_BEAT_BITS) bus_cmd_beat_ff ( rvdffs #(pt.ICACHE_BEAT_BITS) bus_cmd_beat_ff (
.*, .*,
.clk(busclk_reset), .clk(busclk_reset),
.clken(bus_ifu_bus_clk_en | ic_act_miss_f | dec_tlu_force_halt),
.rawclk(clk),
.en(bus_cmd_beat_en), .en(bus_cmd_beat_en),
.din({bus_new_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]}), .din({bus_new_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]}),
.dout({bus_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]}) .dout({bus_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]})
@ -1715,11 +1681,9 @@ module el2_ifu_mem_ctl
for (genvar j = 0; j < 8; j++) begin : WAY_STATUS for (genvar j = 0; j < 8; j++) begin : WAY_STATUS
rvdffs_fpga #(pt.ICACHE_STATUS_BITS) ic_way_status ( rvdffs #(pt.ICACHE_STATUS_BITS) ic_way_status (
.*, .*,
.clk(way_status_clk[i]), .clk(way_status_clk[i]),
.clken(way_status_clken[i]),
.rawclk(clk),
.en(((ifu_status_wr_addr_ff[pt.ICACHE_TAG_INDEX_LO+2:pt.ICACHE_TAG_INDEX_LO] == j) & way_status_wr_en_ff)), .en(((ifu_status_wr_addr_ff[pt.ICACHE_TAG_INDEX_LO+2:pt.ICACHE_TAG_INDEX_LO] == j) & way_status_wr_en_ff)),
.din(way_status_new_ff[pt.ICACHE_STATUS_BITS-1:0]), .din(way_status_new_ff[pt.ICACHE_STATUS_BITS-1:0]),
.dout(way_status_out[8*i+j]) .dout(way_status_out[8*i+j])
@ -1782,11 +1746,9 @@ module el2_ifu_mem_ctl
for (genvar k = 0; k < 32; k++) begin : TAG_VALID for (genvar k = 0; k < 32; k++) begin : TAG_VALID
rvdffs_fpga #(1) ic_way_tagvalid_dup ( rvdffs #(1) ic_way_tagvalid_dup (
.*, .*,
.clk(tag_valid_clk[i][j]), .clk(tag_valid_clk[i][j]),
.clken(tag_valid_clken[i][j]),
.rawclk(clk),
.en(((ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (k + 32*i)) & ifu_tag_wren_ff[j] ) | .en(((ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (k + 32*i)) & ifu_tag_wren_ff[j] ) |
((perr_ic_index_ff [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (k + 32*i)) & perr_err_inv_way[j]) | reset_all_tags), ((perr_ic_index_ff [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == (k + 32*i)) & perr_err_inv_way[j]) | reset_all_tags),
.din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate), .din(ic_valid_ff & ~reset_all_tags & ~perr_sel_invalidate),
@ -1945,11 +1907,9 @@ module el2_ifu_mem_ctl
assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array; assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array;
rvdff_fpga #(01 + pt.ICACHE_NUM_WAYS) ifu_debug_sel_ff ( rvdff #(01 + pt.ICACHE_NUM_WAYS) ifu_debug_sel_ff (
.*, .*,
.clk(debug_c1_clk), .clk(debug_c1_clk),
.clken(debug_c1_clken),
.rawclk(clk),
.din({ic_debug_ict_array_sel_in, ic_debug_way[pt.ICACHE_NUM_WAYS-1:0]}), .din({ic_debug_ict_array_sel_in, ic_debug_way[pt.ICACHE_NUM_WAYS-1:0]}),
.dout({ic_debug_ict_array_sel_ff, ic_debug_way_ff[pt.ICACHE_NUM_WAYS-1:0]}) .dout({ic_debug_ict_array_sel_ff, ic_debug_way_ff[pt.ICACHE_NUM_WAYS-1:0]})
); );

108
Flow/design/lib/beh_lib.sv
View File

@ -29,13 +29,8 @@ module rvdff #(
if (SHORT == 1) begin if (SHORT == 1) begin
assign dout = din; assign dout = din;
end else begin
`ifdef RV_CLOCKGATE
always @(posedge tb_top.clk) begin
#0 $strobe("CG: %0t %m din %x dout %x clk %b width %d", $time, din, dout, clk, WIDTH);
end end
`endif else begin
always_ff @(posedge clk or negedge rst_l) begin always_ff @(posedge clk or negedge rst_l) begin
if (rst_l == 0) dout[WIDTH-1:0] <= 0; if (rst_l == 0) dout[WIDTH-1:0] <= 0;
else dout[WIDTH-1:0] <= din[WIDTH-1:0]; else dout[WIDTH-1:0] <= din[WIDTH-1:0];
@ -92,75 +87,6 @@ module rvdffsc #(
end end
endmodule endmodule
// _fpga versions
module rvdff_fpga #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin
assign dout = din;
end else begin
rvdff #(WIDTH) dff (.*);
end
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs_fpga #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin : genblock
assign dout = din;
end else begin : genblock
rvdffs #(WIDTH) dffs (.*);
end
endmodule
// rvdff with en and clear
module rvdffsc_fpga #(
parameter WIDTH = 1,
SHORT = 0
) (
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
assign dout = din;
end else begin
rvdffsc #(WIDTH) dffsc (.*);
end
endmodule
module rvdffe #( module rvdffe #(
parameter WIDTH = 1, parameter WIDTH = 1,
SHORT = 0, SHORT = 0,
@ -366,38 +292,6 @@ module rvsyncss #(
endmodule // rvsyncss endmodule // rvsyncss
module rvsyncss_fpga #(
parameter WIDTH = 251
) (
input logic gw_clk,
input logic rawclk,
input logic clken,
input logic rst_l,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_ff1;
rvdff_fpga #(WIDTH) sync_ff1 (
.*,
.clk(gw_clk),
.rawclk(rawclk),
.clken(clken),
.din(din[WIDTH-1:0]),
.dout(din_ff1[WIDTH-1:0])
);
rvdff_fpga #(WIDTH) sync_ff2 (
.*,
.clk(gw_clk),
.rawclk(rawclk),
.clken(clken),
.din(din_ff1[WIDTH-1:0]),
.dout(dout[WIDTH-1:0])
);
endmodule // rvsyncss
module rvlsadder ( module rvlsadder (
input logic [31:0] rs1, input logic [31:0] rs1,
input logic [11:0] offset, input logic [11:0] offset,

104
Flow/design/lsu/el2_lsu_bus_buffer.sv
View File

@ -647,14 +647,12 @@ module el2_lsu_bus_buffer
(ibuf_buf_byp & ldst_samedw_r & ldst_dual_r); (ibuf_buf_byp & ldst_samedw_r & ldst_dual_r);
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) obuf_wren_ff ( ) obuf_wren_ff (
.din(obuf_wr_en), .din(obuf_wr_en),
.dout(obuf_wr_enQ), .dout(obuf_wr_enQ),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdffsc #( rvdffsc #(
@ -685,111 +683,91 @@ module el2_lsu_bus_buffer
.clk (lsu_free_c2_clk), .clk (lsu_free_c2_clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) obuf_cmd_done_ff ( ) obuf_cmd_done_ff (
.din(obuf_cmd_done_in), .din(obuf_cmd_done_in),
.dout(obuf_cmd_done), .dout(obuf_cmd_done),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) obuf_data_done_ff ( ) obuf_data_done_ff (
.din(obuf_data_done_in), .din(obuf_data_done_in),
.dout(obuf_data_done), .dout(obuf_data_done),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(pt.LSU_BUS_TAG) .WIDTH(pt.LSU_BUS_TAG)
) obuf_rdrsp_tagff ( ) obuf_rdrsp_tagff (
.din(obuf_rdrsp_tag_in), .din(obuf_rdrsp_tag_in),
.dout(obuf_rdrsp_tag), .dout(obuf_rdrsp_tag),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(pt.LSU_BUS_TAG) .WIDTH(pt.LSU_BUS_TAG)
) obuf_tag0ff ( ) obuf_tag0ff (
.din(obuf_tag0_in), .din(obuf_tag0_in),
.dout(obuf_tag0), .dout(obuf_tag0),
.en(obuf_wr_en), .en(obuf_wr_en),
.clk(lsu_bus_obuf_c1_clk), .clk(lsu_bus_obuf_c1_clk),
.clken(lsu_bus_obuf_c1_clken),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(pt.LSU_BUS_TAG) .WIDTH(pt.LSU_BUS_TAG)
) obuf_tag1ff ( ) obuf_tag1ff (
.din(obuf_tag1_in), .din(obuf_tag1_in),
.dout(obuf_tag1), .dout(obuf_tag1),
.en(obuf_wr_en), .en(obuf_wr_en),
.clk(lsu_bus_obuf_c1_clk), .clk(lsu_bus_obuf_c1_clk),
.clken(lsu_bus_obuf_c1_clken),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(1) .WIDTH(1)
) obuf_mergeff ( ) obuf_mergeff (
.din(obuf_merge_in), .din(obuf_merge_in),
.dout(obuf_merge), .dout(obuf_merge),
.en(obuf_wr_en), .en(obuf_wr_en),
.clk(lsu_bus_obuf_c1_clk), .clk(lsu_bus_obuf_c1_clk),
.clken(lsu_bus_obuf_c1_clken),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(1) .WIDTH(1)
) obuf_writeff ( ) obuf_writeff (
.din(obuf_write_in), .din(obuf_write_in),
.dout(obuf_write), .dout(obuf_write),
.en(obuf_wr_en), .en(obuf_wr_en),
.clk(lsu_bus_obuf_c1_clk), .clk(lsu_bus_obuf_c1_clk),
.clken(lsu_bus_obuf_c1_clken),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(1) .WIDTH(1)
) obuf_sideeffectff ( ) obuf_sideeffectff (
.din(obuf_sideeffect_in), .din(obuf_sideeffect_in),
.dout(obuf_sideeffect), .dout(obuf_sideeffect),
.en(obuf_wr_en), .en(obuf_wr_en),
.clk(lsu_bus_obuf_c1_clk), .clk(lsu_bus_obuf_c1_clk),
.clken(lsu_bus_obuf_c1_clken),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(2) .WIDTH(2)
) obuf_szff ( ) obuf_szff (
.din(obuf_sz_in[1:0]), .din(obuf_sz_in[1:0]),
.dout(obuf_sz), .dout(obuf_sz),
.en(obuf_wr_en), .en(obuf_wr_en),
.clk(lsu_bus_obuf_c1_clk), .clk(lsu_bus_obuf_c1_clk),
.clken(lsu_bus_obuf_c1_clken),
.rawclk(clk),
.* .*
); );
rvdffs_fpga #( rvdffs #(
.WIDTH(8) .WIDTH(8)
) obuf_byteenff ( ) obuf_byteenff (
.din(obuf_byteen_in[7:0]), .din(obuf_byteen_in[7:0]),
.dout(obuf_byteen), .dout(obuf_byteen),
.en(obuf_wr_en), .en(obuf_wr_en),
.clk(lsu_bus_obuf_c1_clk), .clk(lsu_bus_obuf_c1_clk),
.clken(lsu_bus_obuf_c1_clken),
.rawclk(clk),
.* .*
); );
rvdffe #( rvdffe #(
@ -808,14 +786,12 @@ module el2_lsu_bus_buffer
.en (obuf_wr_en), .en (obuf_wr_en),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(TIMER_LOG2) .WIDTH(TIMER_LOG2)
) obuf_timerff ( ) obuf_timerff (
.din(obuf_wr_timer_in), .din(obuf_wr_timer_in),
.dout(obuf_wr_timer), .dout(obuf_wr_timer),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
@ -1312,105 +1288,85 @@ module el2_lsu_bus_buffer
assign lsu_pmu_bus_error = lsu_imprecise_error_load_any | lsu_imprecise_error_store_any; assign lsu_pmu_bus_error = lsu_imprecise_error_load_any | lsu_imprecise_error_store_any;
assign lsu_pmu_bus_busy = (lsu_axi_awvalid & ~lsu_axi_awready) | (lsu_axi_wvalid & ~lsu_axi_wready) | (lsu_axi_arvalid & ~lsu_axi_arready); assign lsu_pmu_bus_busy = (lsu_axi_awvalid & ~lsu_axi_awready) | (lsu_axi_wvalid & ~lsu_axi_wready) | (lsu_axi_arvalid & ~lsu_axi_arready);
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_awvalid_ff ( ) lsu_axi_awvalid_ff (
.din(lsu_axi_awvalid), .din(lsu_axi_awvalid),
.dout(lsu_axi_awvalid_q), .dout(lsu_axi_awvalid_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_awready_ff ( ) lsu_axi_awready_ff (
.din(lsu_axi_awready), .din(lsu_axi_awready),
.dout(lsu_axi_awready_q), .dout(lsu_axi_awready_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_wvalid_ff ( ) lsu_axi_wvalid_ff (
.din(lsu_axi_wvalid), .din(lsu_axi_wvalid),
.dout(lsu_axi_wvalid_q), .dout(lsu_axi_wvalid_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_wready_ff ( ) lsu_axi_wready_ff (
.din(lsu_axi_wready), .din(lsu_axi_wready),
.dout(lsu_axi_wready_q), .dout(lsu_axi_wready_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_arvalid_ff ( ) lsu_axi_arvalid_ff (
.din(lsu_axi_arvalid), .din(lsu_axi_arvalid),
.dout(lsu_axi_arvalid_q), .dout(lsu_axi_arvalid_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_arready_ff ( ) lsu_axi_arready_ff (
.din(lsu_axi_arready), .din(lsu_axi_arready),
.dout(lsu_axi_arready_q), .dout(lsu_axi_arready_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_bvalid_ff ( ) lsu_axi_bvalid_ff (
.din(lsu_axi_bvalid), .din(lsu_axi_bvalid),
.dout(lsu_axi_bvalid_q), .dout(lsu_axi_bvalid_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_bready_ff ( ) lsu_axi_bready_ff (
.din(lsu_axi_bready), .din(lsu_axi_bready),
.dout(lsu_axi_bready_q), .dout(lsu_axi_bready_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(2) .WIDTH(2)
) lsu_axi_bresp_ff ( ) lsu_axi_bresp_ff (
.din(lsu_axi_bresp[1:0]), .din(lsu_axi_bresp[1:0]),
.dout(lsu_axi_bresp_q[1:0]), .dout(lsu_axi_bresp_q[1:0]),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(pt.LSU_BUS_TAG) .WIDTH(pt.LSU_BUS_TAG)
) lsu_axi_bid_ff ( ) lsu_axi_bid_ff (
.din(lsu_axi_bid[pt.LSU_BUS_TAG-1:0]), .din(lsu_axi_bid[pt.LSU_BUS_TAG-1:0]),
.dout(lsu_axi_bid_q[pt.LSU_BUS_TAG-1:0]), .dout(lsu_axi_bid_q[pt.LSU_BUS_TAG-1:0]),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdffe #( rvdffe #(
@ -1422,44 +1378,36 @@ module el2_lsu_bus_buffer
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_rvalid_ff ( ) lsu_axi_rvalid_ff (
.din(lsu_axi_rvalid), .din(lsu_axi_rvalid),
.dout(lsu_axi_rvalid_q), .dout(lsu_axi_rvalid_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(1) .WIDTH(1)
) lsu_axi_rready_ff ( ) lsu_axi_rready_ff (
.din(lsu_axi_rready), .din(lsu_axi_rready),
.dout(lsu_axi_rready_q), .dout(lsu_axi_rready_q),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(2) .WIDTH(2)
) lsu_axi_rresp_ff ( ) lsu_axi_rresp_ff (
.din(lsu_axi_rresp[1:0]), .din(lsu_axi_rresp[1:0]),
.dout(lsu_axi_rresp_q[1:0]), .dout(lsu_axi_rresp_q[1:0]),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );
rvdff_fpga #( rvdff #(
.WIDTH(pt.LSU_BUS_TAG) .WIDTH(pt.LSU_BUS_TAG)
) lsu_axi_rid_ff ( ) lsu_axi_rid_ff (
.din(lsu_axi_rid[pt.LSU_BUS_TAG-1:0]), .din(lsu_axi_rid[pt.LSU_BUS_TAG-1:0]),
.dout(lsu_axi_rid_q[pt.LSU_BUS_TAG-1:0]), .dout(lsu_axi_rid_q[pt.LSU_BUS_TAG-1:0]),
.clk(lsu_busm_clk), .clk(lsu_busm_clk),
.clken(lsu_busm_clken),
.rawclk(clk),
.* .*
); );