From fc331027c20074587e3f6c84bb597ec061cadad1 Mon Sep 17 00:00:00 2001
From: Ajay Nath <Ajay.Nath@wdc.com>
Date: Tue, 3 Sep 2019 21:35:43 -0400
Subject: [PATCH] Conditioned declaration of finished per issue #13

---
 testbench/tb_top.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv
index 94c0555..e42ccfb 100644
--- a/testbench/tb_top.sv
+++ b/testbench/tb_top.sv
@@ -100,7 +100,9 @@ module tb_top ( input logic core_clk, input logic reset_l, output finished);
 
    logic        [31:0]                  cycleCnt       ;
    logic                                mailbox_data_val;
+`ifndef VERILATOR
    logic                                finished;
+`endif
 
    wire                                 dma_hready_out;