5 Commits

Author	SHA1	Message	Date
colin	2c4658ddb9	Refine murax sim config file	2022-02-28 03:33:41 +00:00
colin	94c99367ba	remove gen file in fpga	2022-02-27 04:49:27 +00:00
colin	1d1237c223	Add VexRiscv fpga generation to ecp5.	2022-02-26 15:14:43 +00:00
colin	25a557365b	Enable VexRiscv murax jtag simulator by verilator.	2022-02-26 14:34:25 +00:00
colin	65545d5e03	Add VexRiscv.	2022-02-25 11:56:36 +00:00