Joseph Rahmeh
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3820e84e20
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Move declarations to top of Verilog file to fix fpga compile issues.
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2019-10-15 13:14:36 -07:00 |
aprnath
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761e69df4e
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Update release-notes.md
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2019-09-04 17:44:15 -04:00 |
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Joseph Rahmeh
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b35d7e9e1b
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Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
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2019-09-04 13:29:39 -07:00 |
jrahmeh
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189ce25027
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Updated release notes
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2019-08-13 16:42:26 -05:00 |
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jrahmeh
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c5a699aa40
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Fixed release notes
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2019-08-13 15:08:45 -05:00 |
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Joseph Rahmeh
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85a510db19
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Updated release notes.
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2019-08-13 12:43:09 -07:00 |
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Joseph Rahmeh
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e7f57a0d5d
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Added 1.1.1 release notes.
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2019-08-10 13:23:08 -07:00 |
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jrahmeh
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56db557851
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Update release-notes.md
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2019-06-04 11:31:56 -05:00 |
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Joseph Rahmeh
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d33df11a5b
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Added release notes.
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2019-06-04 09:29:22 -07:00 |