Joseph Rahmeh
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ec254f5491
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Version 1.9.
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2021-01-27 09:36:43 -08:00 |
Thomas Wicki
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3c50837a75
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Update release-notes.md
Minor corrections
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2020-09-18 18:00:45 -07:00 |
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Joseph Rahmeh
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5e613582c2
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New branch: branch1.8
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2020-09-18 13:34:02 -07:00 |
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Joseph Rahmeh
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8065eef677
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Branch for version 1.7
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2020-06-25 19:59:36 -07:00 |
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Joseph Rahmeh
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83d5753bad
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Version 1.6
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2020-05-15 11:40:52 -07:00 |
jrahmeh
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91ac750284
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Update release-notes.md
Remove from the 1.5 release notes items that were accidentally carried over from a previous release.
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2020-02-26 19:27:55 -06:00 |
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Joseph Rahmeh
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36675abd25
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Updated release notes.
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2020-02-19 18:18:48 -08:00 |
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Joseph Rahmeh
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480c765eb4
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Cleanup release notes.
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2020-02-19 07:07:31 -08:00 |
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Joseph Rahmeh
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d0c6e56012
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Formatting changes.
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2020-02-18 13:51:15 -08:00 |
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Joseph Rahmeh
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9228e01812
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Added release notes for version 1.5.
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2020-02-18 13:40:11 -08:00 |
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Joseph Rahmeh
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3820e84e20
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Move declarations to top of Verilog file to fix fpga compile issues.
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2019-10-15 13:14:36 -07:00 |
aprnath
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761e69df4e
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Update release-notes.md
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2019-09-04 17:44:15 -04:00 |
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Joseph Rahmeh
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b35d7e9e1b
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Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
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2019-09-04 13:29:39 -07:00 |
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jrahmeh
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189ce25027
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Updated release notes
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2019-08-13 16:42:26 -05:00 |
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jrahmeh
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c5a699aa40
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Fixed release notes
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2019-08-13 15:08:45 -05:00 |
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Joseph Rahmeh
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85a510db19
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Updated release notes.
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2019-08-13 12:43:09 -07:00 |
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Joseph Rahmeh
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e7f57a0d5d
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Added 1.1.1 release notes.
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2019-08-10 13:23:08 -07:00 |
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jrahmeh
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56db557851
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Update release-notes.md
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2019-06-04 11:31:56 -05:00 |
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Joseph Rahmeh
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d33df11a5b
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Added release notes.
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2019-06-04 09:29:22 -07:00 |