6 Commits

Author	SHA1	Message	Date
colin	cffec82632	Add clean before fpga ram make all	2022-02-17 06:21:42 +00:00
colin	18c8352c09	Add ram test and verilator in fpga DEMO.	2022-02-09 12:47:35 +00:00
colin	3c3cfccfd5	add ram test.	2022-02-08 03:00:40 +00:00
colin	a7ef641f0d	Refine io level	2022-02-07 13:34:50 +00:00
colin	3405c88c9e	Correct blink and use sample blink code	2022-02-07 13:23:34 +00:00
colin	3ba8533996	Add fpga	2022-02-02 03:43:53 +00:00