5 Commits

Author	SHA1	Message	Date
Joseph Rahmeh	8065eef677	Branch for version 1.7	2020-06-25 19:59:36 -07:00
Joseph Rahmeh	b65d4dd8f1	Version 1.5	2020-02-19 18:25:04 -08:00
Joseph Rahmeh	b35d7e9e1b	Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.	2019-09-04 13:29:39 -07:00
Joseph Rahmeh	7ff8d7fb5a	Untabified files.	2019-08-13 12:48:48 -07:00
Joseph Rahmeh	c0f7e509cc	SweRV 1.1	2019-06-04 07:57:48 -07:00