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177 Commits

Author SHA1 Message Date
Colin 7aff1ae5f1 add soc for common test with soc. 2022-01-17 11:53:50 +00:00
Colin 3be1146718 refine define file build 2022-01-17 11:40:11 +00:00
Colin 1d8069026b remove no use file in demo 2022-01-17 11:10:22 +00:00
Colin 2b298f0fff rename test to demo 2022-01-17 06:43:14 +00:00
Colin 0eb74fdc10 refine test use function 2022-01-05 03:47:27 +00:00
Colin 6567357739 add llvm build flow from .c file 2022-01-04 12:39:14 +00:00
Colin be63e84a1d Add build from llvm 2021-12-17 13:29:59 +00:00
Colin 911f65874f add test of verilator in one folder 2021-12-16 12:08:59 +00:00
Ajay Nath 87c23b9952
Merge pull request #101 from antmicro/fix-vivado-tcl 
Remove not existing file from vivado.tcl
 2021-10-08 17:45:03 -04:00
Kamil Rakoczy f57cce19ff Remove not existing file from vivado.tcl 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-08-27 15:27:02 +02:00
Ajay Nath 81bff1c0d7 reverting to 0242c9e for swerv_config_gen.py 2021-03-12 08:02:57 -05:00
Ajay Nath d4e7b25f71
Merge pull request #93 from antmicro/variable-order-fix 
Declare variables before using them
Thank you for this update.
 2021-02-19 15:03:43 -05:00
Tomasz Gorochowik 74a6bdb50d Do not use variables before declaration 2021-02-17 17:09:35 +01:00
Ajay Nath f3da044f15
Delete testbench/tests/cmark_dccm directory 
This directory is redundant due to the reworking of test flow in release 1.9
 2021-02-16 08:56:23 -05:00
Thomas Wicki 5e23462bd0
Update README.md 2021-02-03 13:26:41 -08:00
Joseph Rahmeh 695883a674 Removed dead code. 2021-02-03 11:08:48 -08:00
Joseph Rahmeh 0c92ea167b Version 1.9 2021-02-03 07:07:10 -08:00
Joseph Rahmeh ec254f5491 Version 1.9. 2021-01-27 09:36:43 -08:00
Ajay Nath bcb5b33726
Merge pull request #82 from chipsalliance/quartus_core_fix 
Only load Vivado TCL files when using Vivado
 2021-01-21 17:59:41 -05:00
Ajay Nath bb9f9ef37b
Merge pull request #89 from olofk/scan_mode 
Remove unused scan_mode input from dmi_wrapper.
We will be releasing some fixes shortly which will have this change too. Accepting your PR so as not hold up any progress.
 2021-01-21 17:58:36 -05:00
Olof Kindgren bcf505751e Remove unused scan_mode input from dmi_wrapper 
This causes the dmi wrapper from SweRV EH1 and SweRV EL2 to have
the same interface which makes it easier to use the two CPU cores
interchangeably in a design.
 2021-01-18 10:15:08 +01:00
Olof Kindgren 3918a8d345
Only load Vivado TCL files when using Vivado 
This prevents the vivado-specific TCL file to be loaded when using the synth target with other synthesis tools than vivado
 2020-11-24 09:31:52 +01:00
Ajay Nath 7332edc0ad
Merge pull request #76 from olofk/snapshot_dir2 
Set snapshot dir to a known location in FuseSoC SweRV config generator
 2020-09-24 10:26:32 -04:00
Olof Kindgren 0242c9e6d2 Explicitly use python3 2020-09-24 15:24:30 +02:00
Olof Kindgren 801d0f66f6 Set snapshot dir to a known location in FuseSoC SweRV config generator 
The previous fix for the FuseSoC SweRV config generator was not complete
 2020-09-24 14:32:08 +02:00
Ajay Nath 1e8c6e3813
Merge pull request #75 from olofk/snapshot_dir 
Adapt FuseSoC SweRV config generator wrt new snapshot dir
 2020-09-22 13:41:35 -04:00
Olof Kindgren 2627ccc82b Adapt FuseSoC SweRV config generator wrt new snapshot dir 2020-09-22 16:27:04 +02:00
Ajay Nath f32b634c16 Updated per issue #70 2020-09-22 09:58:03 -04:00
Thomas Wicki 3c50837a75
Update release-notes.md 
Minor corrections
 2020-09-18 18:00:45 -07:00
Joseph Rahmeh e63dfe17d8 Updated version in swerv.core 2020-09-18 14:42:34 -07:00
Joseph Rahmeh d6024bcc6b Updated branch number in README file. 2020-09-18 14:08:43 -07:00
Joseph Rahmeh d395a96492 Updated branch number in README file. 2020-09-18 14:03:24 -07:00
Joseph Rahmeh 8caf5f69b0 Added testbench/hex directory. 2020-09-18 13:47:53 -07:00
Joseph Rahmeh 95e9589446 Updated PRM. 2020-09-18 13:47:21 -07:00
Joseph Rahmeh 5e613582c2 New branch: branch1.8 2020-09-18 13:34:02 -07:00
jrahmeh 499378d0c6
Merge pull request #68 from olofk/fusesoc_v1_7 
Update SweRV version in core description file to 1.7
 2020-08-19 12:03:59 -05:00
Olof Kindgren 9e0aeed92e Update SweRV version in core description file to 1.7 2020-08-19 18:25:32 +02:00
Thomas Wicki 48f01f101e
Update README.md 2020-06-26 15:02:13 -07:00
Joseph Rahmeh 5f905a0912 Upped version. 2020-06-26 10:24:06 -07:00
Joseph Rahmeh ae1b1bccad Updated PRM. 2020-06-26 09:55:56 -07:00
Joseph Rahmeh 8065eef677 Branch for version 1.7 2020-06-25 19:59:36 -07:00
Joseph Rahmeh 0555dd8763 Reverted change related to enum assign as it broke some Verilog tools. 2020-05-27 14:50:39 -07:00
jrahmeh 5a004dd2b6
Merge pull request #55 from dawidzim/riviera_fusesoc 
update swerv.core for Riviera-PRO
 2020-05-27 10:55:32 -05:00
jrahmeh 27507b79a1
Merge pull request #49 from dawidzim/enum_from_diff_type 
fix for assignment to enum variable from expression of different type
 2020-05-27 08:38:13 -05:00
Dawid Zimonczyk 23c6ce84dc update swerv.core for Riviera-PRO 2020-05-26 15:17:59 +02:00
Zvonimir Bandic ee7473ee90
SweRV core roadmap white paper 2020-05-20 18:23:44 -07:00
tmw-wdc a4cc4368ad Update RISC-V_SweRV_EH1_PRM.pdf 
Fixed typo in Section 18.3.
 2020-05-15 15:22:32 -07:00
Thomas Wicki 977175e264
Add 'V' to to title 2020-05-15 14:21:49 -07:00
Thomas Wicki 0b2ec70608
Update version from 1.5 to 1.6 2020-05-15 14:20:29 -07:00
Joseph Rahmeh d2a6fac636 Version 1.6 2020-05-15 13:04:43 -07:00