3 Commits

Author	SHA1	Message	Date
colin	cffec82632	Add clean before fpga ram make all	2022-02-17 06:21:42 +00:00
colin	18c8352c09	Add ram test and verilator in fpga DEMO.	2022-02-09 12:47:35 +00:00
colin	3c3cfccfd5	add ram test.	2022-02-08 03:00:40 +00:00