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11 Commits

Author SHA1 Message Date
Joseph Rahmeh d0c6e56012 Formatting changes. 2020-02-18 13:51:15 -08:00
Joseph Rahmeh 9228e01812 Added release notes for version 1.5. 2020-02-18 13:40:11 -08:00
Joseph Rahmeh 3820e84e20 Move declarations to top of Verilog file to fix fpga compile issues. 2019-10-15 13:14:36 -07:00
aprnath 761e69df4e
Update release-notes.md 2019-09-04 17:44:15 -04:00
Joseph Rahmeh b35d7e9e1b Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module. 2019-09-04 13:29:39 -07:00
jrahmeh 189ce25027
Updated release notes 2019-08-13 16:42:26 -05:00
jrahmeh c5a699aa40
Fixed release notes 2019-08-13 15:08:45 -05:00
Joseph Rahmeh 85a510db19 Updated release notes. 2019-08-13 12:43:09 -07:00
Joseph Rahmeh e7f57a0d5d Added 1.1.1 release notes. 2019-08-10 13:23:08 -07:00
jrahmeh 56db557851
Update release-notes.md 2019-06-04 11:31:56 -05:00
Joseph Rahmeh d33df11a5b Added release notes. 2019-06-04 09:29:22 -07:00