#!/bin/bash

# if [ $# -ne 1 -o ! -d "$1" ]; then
# 	echo "Usage: $0 <design>" >&2
# 	exit 1
# fi

set -ex

PWD=$(pwd)
SOC=$PWD/../../soc
design=${1%/}

YOSYS_COARSE=true
YOSYS_GLOBRST=false
YOSYS_SPLITNETS=false
TOP="soc_top"
RTL=$(cat ../../soc/soc_top.mk)

rtl_files=""
for src in $RTL; do
	rtl_files="$rtl_files $SOC/$src"
done

mkdir -p gen
rm -rf gen/*
mkdir gen/design

BUILD_PATH=gen/ PERLLIB=${SOC} ${SOC}/swerv.config -target=default -set iccm_enable

filelist=""
for file in $rtl_files; do
	filelist="$filelist $file"
done
sv2v -Igen -I/home/colin/develop/AbstractAccelerator/Cores-SweRV/design/include \
  gen/common_defines.vh $filelist > gen/soc_top.v

{
	# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
  # for file in $rtl_files; do
	# 	echo "read_verilog -sv -I../../design/include $file"
	# done
	echo "read_verilog gen/soc_top.v"

	if test -n "$TOP"; then
		echo "hierarchy -check -top $TOP"
	else
		echo "hierarchy -check"
	fi
	if $YOSYS_GLOBRST; then
		# insertation of global reset (e.g. for FPGA cores)
		echo "add -global_input globrst 1"
		echo "proc -global_arst globrst"
	fi
	echo "synth -run coarse; opt -fine"
	# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
	if ! $YOSYS_COARSE; then
		echo "memory_map; techmap; opt; abc -dff; clean"
	fi
	if $YOSYS_SPLITNETS; then
		# icarus verilog has a performance problems when there are
		# dependencies between the bits of a long vector
		echo "splitnets; clean"
	fi
	if $YOSYS_COARSE; then
		echo "write_verilog -noexpr -noattr gen/synth.v"
	else
		echo "select -assert-none t:\$[!_]"
		echo "write_verilog -noattr gen/synth.v"
	fi
	echo "synth_ecp5 -top $TOP -json gen/soc.json"
	# echo "synth_xilinx -top $TOP"
} > gen/synth.ys

yosys -v2 -l gen/synth.log gen/synth.ys

nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1  --json gen/soc.json