module soc_sim (
    input bit core_clk
);
  logic rst_l;

  parameter MAX_CYCLES = 1000;
  // parameter MAX_CYCLES = 10_000_000_0;
  int cycleCnt;

  always @(posedge core_clk) begin
    cycleCnt <= cycleCnt + 1;

    if (cycleCnt == MAX_CYCLES) begin
      $display("Hit max cycle count (%0d) .. stopping", cycleCnt);
      $finish;
    end
  end

  assign rst_l = cycleCnt > 5;

  soc_top rvsoc (
      .clk(core_clk),
      .rst(rst_l)
  );


endmodule