// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//

module soc_sim (
    input  bit clk,
    output     jtag_tdo,
    output     jtag_tck,
    output     jtag_tms,
    output     jtag_tdi
);

  wire        rst;

  bit  [31:0] cycleCnt;

  reg         uart_tx;
  wire        uart_rx;
  wire [ 7:0] gpioa;

  reg         jrst_b;
  reg         nrst_b;

  wire [ 7:0] WriteData;

  parameter MAX_CYCLES = 10_000_000_0;

  integer fd;

  always @(posedge clk) begin
    cycleCnt <= cycleCnt + 1;
    if (cycleCnt == MAX_CYCLES) begin
      $display("Hit max cycle count (%0d) .. stopping", cycleCnt);
      $finish;
    end
    if (WriteData[7:0] == 8'hff) begin
      $display("\nFinished by program");
      $display("TEST_PASSED");
      $finish;
    end else if (WriteData[7:0] == 8'h1) begin
      $display("TEST_FAILED");
      $finish;
    end else begin
      $fwrite(fd, "%c", WriteData[7:0]);
      $write("%c", WriteData[7:0]);
    end
  end

  initial begin
    fd = $fopen("console.log", "w");
  end

  initial begin
    jrst_b = 1;
    #100;
    jrst_b = 0;
    #100;
    jrst_b = 1;
  end

  initial begin
    nrst_b = 1;
    #100;
    nrst_b = 0;
    #100;
    nrst_b = 1;
  end

  assign rst = cycleCnt > 5;

  soc rvsoc (
      .i_pad_clk  (clk),
      .i_pad_rst_b(rst),

      .o_pad_jtg_tdo(jtag_tdo),
      .i_pad_jtg_tclk(jtag_tck),
      .i_pad_jtg_tms(jtag_tms),
      .i_pad_jtg_tdi(jtag_tdi),
      .i_pad_jtg_trst_b(jrst_b),
      .i_pad_jtg_nrst_b(nrst_b),
      .i_pad_uart0_sin(uart_tx),
      .o_pad_uart0_sout(uart_rx),
      .b_pad_gpio_porta(gpioa)
  );

  jtagdpi jtagdpi (
      .clk_i (clk),
      .rst_ni(rst),

      .jtag_tck(jtag_tck),
      .jtag_tms(jtag_tms),
      .jtag_tdi(jtag_tdi),
      .jtag_tdo(jtag_tdo),
      .jtag_trst_n(),
      .jtag_srst_n()
  );

endmodule