# Weekend group ## helloworld This a demo for llvm build and sim with verilator. ## jtag This is a demo of jtag simulation by openocd running on verilator. ## install verilator `sudo apt install verilator` ## install openocd ```shell git clone https://github.com/riscv/riscv-openocd.git cd riscv-openocd ./bootstrap ./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink make sudo make install ``` ## may be install sv2v `https://github.com/zachjs/sv2v` ## install ninja `sudo apt-get install -y ninja-build` ## Gen quasar core ```bash git clone https://github.com/Lampro-Mellon/Quasar.git cd tools vim configs/quasar.config # to config the core make clean make conf make sbt_ # Quasar/generated_rtl/quasar_wrapper.sv ``` ## install Bit-Vector ```bash wget https://cpan.metacpan.org/authors/id/S/ST/STBEY/Bit-Vector-7.4.tar.gz tar -xvf cd perl Makefile.PL make sudo make install ``` ## build and install riscv tools * Opetion1 : ```bash # build 64bit sudo make clean ./configure --prefix=/opt/riscv sudo make -j12 # build 64bit and 32bit sudo make clean ./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d --enable-multilib sudo make -j12 ``` * Opetion2 : ```bash sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev device-tree-compiler pkg-config libexpat-dev libfl-dev git clone https://github.com/chipsalliance/rocket-tools.git git submodule update --init --recursive # riscv-isa-sim and openocd may be checkout to main branch to avoid compile error sudo su export RISCV=/opt/riscv export MAKEFLAGS="-j12" ./build-rv32ima.sh ``` ## install xilinx 1. 下载vivado安装文件 2. 下载vivado lisence 3. 解压vivado的安装文件,sudo执行xsetup开始安装 4. 安装vivado之后,安装 Hardware Server 5. 通过执行安装路径的bin目录的vivado来启动 6. 安装Xilinx Platform Cable USB II 下载器驱动 1. cd /tools/Xilinx/Vivado/2021.2/data/xicom/cable_drivers/lin64/install_script/install_drivers 2. sudo ./install_drivers 3. lsusb 检查安装的usb设备 4. 重新拔插后显示 Bus 005 Device 011: ID 03fd:0008 Xilinx, Inc. Platform Cable USB II ## tips * jtag的reset引脚要设置正确 jtag_trst_n 低电平复位 * 仿真的时候jtag的tclk不能太快,要低于soc的clk * SweRV启动/复位后程序从`reset_vec`(0x80000000)开始,遇到错误(code=0),就会跳到mtvec(中断向量表)指示的地址 * 物理仿真的时候 adapter speed 不能太快 * data段放到0x200太小,GDB调试RISCV至少要4K的程序空间? * soc的ram和rom直接接到了lsu和ifu,和DCCM/ICCM无关 * program.hex 用于 $readmemh 必须以空行结束 ## Todo * gdb怎么复位soc * gdb没有把程序加载到mem,ifu还是用老代码 * mem分bank后,怎么加载,用于仿真=>for循环分别加载 * Quasar升级scala版本发现openocd运行不正常