// SPDX-License-Identifier: Apache-2.0 // Copyright 2020 Western Digital Corporation or its affiliates. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // module soc_top ( input clk, input dbg_rst, input rst, output jtag_tdo, input jtag_tck, input jtag_tms, input jtag_tdi, input jtag_trst_n ); logic nmi_int; logic [31:0] reset_vector; logic [31:0] nmi_vector; logic [31:1] jtag_id; logic [31:0] ic_haddr; logic [ 2:0] ic_hburst; logic ic_hmastlock; logic [ 3:0] ic_hprot; logic [ 2:0] ic_hsize; logic [ 1:0] ic_htrans; logic ic_hwrite; logic [63:0] ic_hrdata; logic ic_hready; logic ic_hresp; logic [31:0] lsu_haddr; logic [ 2:0] lsu_hburst; logic lsu_hmastlock; logic [ 3:0] lsu_hprot; logic [ 2:0] lsu_hsize; logic [ 1:0] lsu_htrans; logic lsu_hwrite; logic [63:0] lsu_hrdata; logic [63:0] lsu_hwdata; logic lsu_hready; logic lsu_hresp; logic [31:0] sb_haddr; logic [ 2:0] sb_hburst; logic sb_hmastlock; logic [ 3:0] sb_hprot; logic [ 2:0] sb_hsize; logic [ 1:0] sb_htrans; logic sb_hwrite; logic [63:0] sb_hrdata; logic [63:0] sb_hwdata; logic sb_hready; logic sb_hresp; logic [63:0] trace_rv_i_insn_ip; logic [63:0] trace_rv_i_address_ip; logic [ 2:0] trace_rv_i_valid_ip; logic [ 2:0] trace_rv_i_exception_ip; logic [ 4:0] trace_rv_i_ecause_ip; logic [ 2:0] trace_rv_i_interrupt_ip; logic [31:0] trace_rv_i_tval_ip; logic o_debug_mode_status; logic [ 1:0] dec_tlu_perfcnt0; logic [ 1:0] dec_tlu_perfcnt1; logic [ 1:0] dec_tlu_perfcnt2; logic [ 1:0] dec_tlu_perfcnt3; logic o_cpu_halt_ack; logic o_cpu_halt_status; logic o_cpu_run_ack; logic mailbox_write; logic [63:0] dma_hrdata; logic [63:0] dma_hwdata; logic dma_hready; logic dma_hresp; logic mpc_debug_halt_req; logic mpc_debug_run_req; logic mpc_reset_run_req; logic mpc_debug_halt_ack; logic mpc_debug_run_ack; logic debug_brkpt_status; wire dma_hready_out; initial begin jtag_id[31:28] = 4'b1; jtag_id[27:12] = '0; jtag_id[11:1] = 11'h45; reset_vector = 32'h0; nmi_vector = 32'hee000000; nmi_int = 0; $readmemh("program.hex", lmem.mem); $readmemh("program.hex", imem.mem); end swerv_wrapper rvtop ( .rst_l (rst), .dbg_rst_l(dbg_rst), .clk (clk), .rst_vec (reset_vector[31:1]), .nmi_int (nmi_int), .nmi_vec (nmi_vector[31:1]), .jtag_id (jtag_id[31:1]), // RV_BUILD_AHB_LITE START .haddr (ic_haddr), .hburst (ic_hburst), .hmastlock(ic_hmastlock), .hprot (ic_hprot), .hsize (ic_hsize), .htrans (ic_htrans), .hwrite (ic_hwrite), .hrdata(ic_hrdata[63:0]), .hready(ic_hready), .hresp (ic_hresp), //--------------------------------------------------------------- // Debug AHB Master //--------------------------------------------------------------- .sb_haddr (sb_haddr), .sb_hburst (sb_hburst), .sb_hmastlock(sb_hmastlock), .sb_hprot (sb_hprot), .sb_hsize (sb_hsize), .sb_htrans (sb_htrans), .sb_hwrite (sb_hwrite), .sb_hwdata (sb_hwdata), .sb_hrdata(sb_hrdata), .sb_hready(sb_hready), .sb_hresp (sb_hresp), //--------------------------------------------------------------- // LSU AHB Master //--------------------------------------------------------------- .lsu_haddr (lsu_haddr), .lsu_hburst (lsu_hburst), .lsu_hmastlock(lsu_hmastlock), .lsu_hprot (lsu_hprot), .lsu_hsize (lsu_hsize), .lsu_htrans (lsu_htrans), .lsu_hwrite (lsu_hwrite), .lsu_hwdata (lsu_hwdata), .lsu_hrdata(lsu_hrdata[63:0]), .lsu_hready(lsu_hready), .lsu_hresp (lsu_hresp), //--------------------------------------------------------------- // DMA Slave //--------------------------------------------------------------- .dma_haddr ('0), .dma_hburst ('0), .dma_hmastlock('0), .dma_hprot ('0), .dma_hsize ('0), .dma_htrans ('0), .dma_hwrite ('0), .dma_hwdata ('0), .dma_hrdata (dma_hrdata), .dma_hresp (dma_hresp), .dma_hsel (1'b1), .dma_hreadyin (dma_hready_out), .dma_hreadyout(dma_hready_out), // RV_BUILD_AHB_LITE END .timer_int (1'b0), .extintsrc_req('0), .lsu_bus_clk_en(1'b1), .ifu_bus_clk_en(1'b1), .dbg_bus_clk_en(1'b1), .dma_bus_clk_en(1'b1), .trace_rv_i_insn_ip (trace_rv_i_insn_ip), .trace_rv_i_address_ip (trace_rv_i_address_ip), .trace_rv_i_valid_ip (trace_rv_i_valid_ip), .trace_rv_i_exception_ip(trace_rv_i_exception_ip), .trace_rv_i_ecause_ip (trace_rv_i_ecause_ip), .trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip), .trace_rv_i_tval_ip (trace_rv_i_tval_ip), .jtag_tck (jtag_tck), .jtag_tms (jtag_tms), .jtag_tdi (jtag_tdi), .jtag_trst_n(jtag_trst_n), .jtag_tdo (jtag_tdo), .mpc_debug_halt_ack(mpc_debug_halt_ack), .mpc_debug_halt_req(1'b0), .mpc_debug_run_ack (mpc_debug_run_ack), .mpc_debug_run_req (1'b1), .mpc_reset_run_req (1'b1), .debug_brkpt_status(debug_brkpt_status), .i_cpu_halt_req (1'b0), .o_cpu_halt_ack (o_cpu_halt_ack), .o_cpu_halt_status (o_cpu_halt_status), .i_cpu_run_req (1'b0), .o_debug_mode_status(o_debug_mode_status), .o_cpu_run_ack (o_cpu_run_ack), .dec_tlu_perfcnt0(dec_tlu_perfcnt0), .dec_tlu_perfcnt1(dec_tlu_perfcnt1), .dec_tlu_perfcnt2(dec_tlu_perfcnt2), .dec_tlu_perfcnt3(dec_tlu_perfcnt3), .scan_mode (1'b0), .mbist_mode(1'b0) ); ahb_sif imem ( // Inputs .HWDATA(64'h0), .HCLK(clk), .HSEL(1'b1), .HPROT(ic_hprot), .HWRITE(ic_hwrite), .HTRANS(ic_htrans), .HSIZE(ic_hsize), .HREADY(ic_hready), .HRESETn(rst), .HADDR(ic_haddr), .HBURST(ic_hburst), // Outputs .HREADYOUT(ic_hready), .HRESP(ic_hresp), .HRDATA(ic_hrdata[63:0]) ); ahb_sif lmem ( // Inputs .HWDATA(lsu_hwdata), .HCLK(clk), .HSEL(1'b1), .HPROT(lsu_hprot), .HWRITE(lsu_hwrite), .HTRANS(lsu_htrans), .HSIZE(lsu_hsize), .HREADY(lsu_hready), .HRESETn(rst), .HADDR(lsu_haddr), .HBURST(lsu_hburst), // Outputs .HREADYOUT(lsu_hready), .HRESP(lsu_hresp), .HRDATA(lsu_hrdata[63:0]) ); endmodule