module ram_single(dataout, addr, datain, we, clk);
   output[7:0] dataout;
   input [7:0] datain;
   input [10:0] addr;
   input we, clk;
   reg [7:0] mem [2048:0];
    always @(posedge clk) begin
        if (we)
            mem[addr] <= datain;
        dataout <= mem[addr];
   end
endmodule

module ram (
    input      clk_i,
    output reg led_o
);
localparam MAX = 2_500_000_0;
localparam WIDTH = $clog2(MAX);


wire[7:0] dataout;
reg[7:0] datain;
reg[10:0] addr;
reg we;

ram_single mem(.dataout(dataout), .addr(addr), .datain(datain), .we(we), .clk(clk_i));


wire clk_s;
assign clk_s = clk_i;

reg  [WIDTH-1:0] cpt_s;
wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
wire             end_s = cpt_s == MAX-1;

wire nextAddr = addr + 1'b1;
wire dataAdd = dataout + 1'b1;
 
always @(posedge clk_s) begin
	cpt_s <= cpt_next_s;
    addr <= nextAddr;
    datain <= dataAdd;

    led_o <= dataout[0];
    // if (end_s)
    //     led_o <= ~led_o;
end
endmodule