{ "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { "xci_name": "mult_gen_0", "component_reference": "xilinx.com:ip:mult_gen:12.0", "ip_revision": "18", "gen_directory": "../../../../zynq7mb_test.gen/sources_1/ip/mult_gen_0", "parameters": { "component_parameters": { "InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "Component_Name": [ { "value": "mult_gen_0", "resolve_type": "user", "usage": "all" } ], "MultType": [ { "value": "Parallel_Multiplier", "resolve_type": "user", "usage": "all" } ], "PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ], "PortAWidth": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ], "PortBType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ], "PortBWidth": [ { "value": "18", "resolve_type": "user", "format": "long", "usage": "all" } ], "ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ], "CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ], "Multiplier_Construction": [ { "value": "Use_LUTs", "resolve_type": "user", "usage": "all" } ], "OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ], "Use_Custom_Output_Width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "OutputWidthHigh": [ { "value": "35", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "OutputWidthLow": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "PipeStages": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], "ClockEnable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "SyncClear": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] }, "model_parameters": { "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ], "C_HAS_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_B_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_B_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_OUT_HIGH": [ { "value": "35", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_OUT_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ], "C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { "ARCHITECTURE": [ { "value": "zynq" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], "DEVICE": [ { "value": "xc7z010" } ], "PACKAGE": [ { "value": "clg400" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2" } ], "STATIC_POWER": [ { "value": "" } ], "TEMPERATURE_GRADE": [ { "value": "" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], "OUTPUTDIR": [ { "value": "../../../../zynq7mb_test.gen/sources_1/ip/mult_gen_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, "boundary": { "ports": { "CLK": [ { "direction": "in", "driver_value": "0x1" } ], "A": [ { "direction": "in", "size_left": "17", "size_right": "0", "driver_value": "0" } ], "B": [ { "direction": "in", "size_left": "17", "size_right": "0", "driver_value": "0" } ], "P": [ { "direction": "out", "size_left": "35", "size_right": "0", "driver_value": "0" } ] }, "interfaces": { "a_intf": { "vlnv": "xilinx.com:signal:data:1.0", "abstraction_type": "xilinx.com:signal:data_rtl:1.0", "mode": "slave", "parameters": { "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "DATA": [ { "physical_name": "A" } ] } }, "clk_intf": { "vlnv": "xilinx.com:signal:clock:1.0", "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { "ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ], "ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ], "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "CLK": [ { "physical_name": "CLK" } ] } }, "sclr_intf": { "vlnv": "xilinx.com:signal:reset:1.0", "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", "mode": "slave", "parameters": { "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] } }, "ce_intf": { "vlnv": "xilinx.com:signal:clockenable:1.0", "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", "mode": "slave", "parameters": { "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] } }, "b_intf": { "vlnv": "xilinx.com:signal:data:1.0", "abstraction_type": "xilinx.com:signal:data_rtl:1.0", "mode": "slave", "parameters": { "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "DATA": [ { "physical_name": "B" } ] } }, "p_intf": { "vlnv": "xilinx.com:signal:data:1.0", "abstraction_type": "xilinx.com:signal:data_rtl:1.0", "mode": "master", "parameters": { "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { "DATA": [ { "physical_name": "P" } ] } } } } } }