# Project configuration -------------------------------------------------------

create_project -force vivado
set_property SOURCE_MGMT_MODE None [current_project]
set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
set_property PART xc7z010-2-clg400 [current_project]

# Files inclusion

add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/TOP.v

add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/led.v

add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/design_1/design_1.bd
add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/mult_gen_0.xci

# Constraints inclusion

add_file -fileset constrs_1 /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc
set_property TARGET_CONSTRS_FILE /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc [current_fileset -constrset]

add_file -fileset constrs_1 /home/colin/develop/abstractaccelerator/fpga/xc7z010/pin.xdc

# Top-level specification
set_property TOP TOP [current_fileset]

# Verilog Includes
set_property INCLUDE_DIRS { /home/colin/develop/abstractaccelerator/fpga/xc7z010 } [current_fileset]

# Verilog Parameters / VHDL Generics
set_property GENERIC { FREQ=125000000 SECS=1 } -objects [get_filesets sources_1]


close_project

# Design flow -----------------------------------------------------------------

open_project vivado

# Synthesis

# PRESYNTH
# set_property DESIGN_MODE GateLvl [current_fileset]
reset_run synth_1
launch_runs synth_1
wait_on_run synth_1
#report_property [get_runs synth_1]
if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }

# Place and Route

reset_run impl_1
launch_runs impl_1
wait_on_run impl_1
#report_property [get_runs impl_1]
if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }

# Bitstream generation

open_run impl_1
write_bitstream -force vivado
write_debug_probes -force -quiet vivado.ltx

close_project