from pyfpga.vivado import Vivado

prj = Vivado(odir=f'./build')

prj.set_part('xc7z010-2-clg400')
prj.add_param('FREQ', '125000000')
prj.add_cons('timing.xdc')
prj.add_cons('pin.xdc')
prj.add_param('SECS', '1')

prj.add_include('./')
prj.add_vlog('*.v')
prj.add_vlog('./design_1/design_1.bd')

prj.set_top('TOP')

prj.make()
prj.prog()