`timescale 1ns/1ps


module soc (
  input  wire          io_asyncReset,
  input  wire          io_mainClk,
  input  wire [31:0]   io_gpioA_read,
  output wire [31:0]   io_gpioA_write,
  output wire [31:0]   io_gpioA_writeEnable,
  output wire          io_uart_txd,
  input  wire          io_uart_rxd
);

wire  jtag_tck;
wire  jtag_tms;
wire  jtag_tdi;
wire  jtag_tdo;

bit    [31:0] cycleCnt;
always @(posedge io_mainClk) begin
  cycleCnt <= cycleCnt + 1;
end

wire clk;
assign clk = cycleCnt[2];
logic  rst_l;
assign rst_l = cycleCnt > 100;

Murax murax(
  .io_asyncReset(io_asyncReset),
  .io_mainClk(io_mainClk),

  .io_jtag_tms(jtag_tms),
  .io_jtag_tdi(jtag_tdi),
  .io_jtag_tdo(jtag_tdo),
  .io_jtag_tck(jtag_tck),

  .io_gpioA_read(io_gpioA_read),
  .io_gpioA_write(io_gpioA_write),
  .io_gpioA_writeEnable(io_gpioA_writeEnable),
  .io_uart_txd(io_uart_txd),
  .io_uart_rxd(io_uart_rxd)
);

jtagdpi jtagdpi (
  .clk_i (io_mainClk),
  .rst_ni(rst_l),

  .jtag_tck(jtag_tck),
  .jtag_tms(jtag_tms),
  .jtag_tdi(jtag_tdi),
  .jtag_tdo(jtag_tdo),
  .jtag_trst_n(),
  .jtag_srst_n()
);

endmodule