708 lines
23 KiB
Systemverilog
708 lines
23 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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module soc_top (
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input clk,
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input dbg_rst,
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input rst,
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output jtag_tdo,
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input jtag_tck,
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input jtag_tms,
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input jtag_tdi,
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input jtag_trst_n
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);
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logic nmi_int;
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logic [ 31:0] reset_vector;
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logic [ 31:0] nmi_vector;
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logic [ 31:1] jtag_id;
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logic [ 31:0] ic_haddr;
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logic [ 2:0] ic_hburst;
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logic ic_hmastlock;
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logic [ 3:0] ic_hprot;
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logic [ 2:0] ic_hsize;
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logic [ 1:0] ic_htrans;
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logic ic_hwrite;
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logic [ 63:0] ic_hrdata;
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logic ic_hready;
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logic ic_hresp;
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logic [ 31:0] lsu_haddr;
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logic [ 2:0] lsu_hburst;
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logic lsu_hmastlock;
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logic [ 3:0] lsu_hprot;
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logic [ 2:0] lsu_hsize;
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logic [ 1:0] lsu_htrans;
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logic lsu_hwrite;
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logic [ 63:0] lsu_hrdata;
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logic [ 63:0] lsu_hwdata;
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logic lsu_hready;
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logic lsu_hresp;
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logic [ 31:0] sb_haddr;
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logic [ 2:0] sb_hburst;
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logic sb_hmastlock;
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logic [ 3:0] sb_hprot;
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logic [ 2:0] sb_hsize;
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logic [ 1:0] sb_htrans;
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logic sb_hwrite;
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logic [ 63:0] sb_hrdata;
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logic [ 63:0] sb_hwdata;
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logic sb_hready;
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logic sb_hresp;
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logic [ 63:0] trace_rv_i_insn_ip;
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logic [ 63:0] trace_rv_i_address_ip;
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logic [ 2:0] trace_rv_i_valid_ip;
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logic [ 2:0] trace_rv_i_exception_ip;
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logic [ 4:0] trace_rv_i_ecause_ip;
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logic [ 2:0] trace_rv_i_interrupt_ip;
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logic [ 31:0] trace_rv_i_tval_ip;
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logic o_debug_mode_status;
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logic [ 1:0] dec_tlu_perfcnt0;
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logic [ 1:0] dec_tlu_perfcnt1;
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logic [ 1:0] dec_tlu_perfcnt2;
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logic [ 1:0] dec_tlu_perfcnt3;
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logic o_cpu_halt_ack;
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logic o_cpu_halt_status;
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logic o_cpu_run_ack;
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logic mailbox_write;
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logic [ 63:0] dma_hrdata;
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logic [ 63:0] dma_hwdata;
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logic dma_hready;
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logic dma_hresp;
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logic mpc_debug_halt_req;
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logic mpc_debug_run_req;
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logic mpc_reset_run_req;
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logic mpc_debug_halt_ack;
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logic mpc_debug_run_ack;
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logic debug_brkpt_status;
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wire dma_hready_out;
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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wire lsu_axi_awvalid;
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wire lsu_axi_awready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid;
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wire [ 31:0] lsu_axi_awaddr;
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wire [ 3:0] lsu_axi_awregion;
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wire [ 7:0] lsu_axi_awlen;
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wire [ 2:0] lsu_axi_awsize;
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wire [ 1:0] lsu_axi_awburst;
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wire lsu_axi_awlock;
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wire [ 3:0] lsu_axi_awcache;
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wire [ 2:0] lsu_axi_awprot;
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wire [ 3:0] lsu_axi_awqos;
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wire lsu_axi_wvalid;
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wire lsu_axi_wready;
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wire [ 63:0] lsu_axi_wdata;
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wire [ 7:0] lsu_axi_wstrb;
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wire lsu_axi_wlast;
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wire lsu_axi_bvalid;
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wire lsu_axi_bready;
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wire [ 1:0] lsu_axi_bresp;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid;
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// AXI Read Channels
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wire lsu_axi_arvalid;
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wire lsu_axi_arready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid;
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wire [ 31:0] lsu_axi_araddr;
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wire [ 3:0] lsu_axi_arregion;
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wire [ 7:0] lsu_axi_arlen;
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wire [ 2:0] lsu_axi_arsize;
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wire [ 1:0] lsu_axi_arburst;
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wire lsu_axi_arlock;
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wire [ 3:0] lsu_axi_arcache;
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wire [ 2:0] lsu_axi_arprot;
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wire [ 3:0] lsu_axi_arqos;
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wire lsu_axi_rvalid;
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wire lsu_axi_rready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid;
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wire [ 63:0] lsu_axi_rdata;
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wire [ 1:0] lsu_axi_rresp;
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wire lsu_axi_rlast;
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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wire ifu_axi_awvalid;
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wire ifu_axi_awready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid;
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wire [ 31:0] ifu_axi_awaddr;
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wire [ 3:0] ifu_axi_awregion;
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wire [ 7:0] ifu_axi_awlen;
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wire [ 2:0] ifu_axi_awsize;
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wire [ 1:0] ifu_axi_awburst;
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wire ifu_axi_awlock;
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wire [ 3:0] ifu_axi_awcache;
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wire [ 2:0] ifu_axi_awprot;
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wire [ 3:0] ifu_axi_awqos;
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wire ifu_axi_wvalid;
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wire ifu_axi_wready;
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wire [ 63:0] ifu_axi_wdata;
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wire [ 7:0] ifu_axi_wstrb;
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wire ifu_axi_wlast;
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wire ifu_axi_bvalid;
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wire ifu_axi_bready;
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wire [ 1:0] ifu_axi_bresp;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid;
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// AXI Read Channels
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wire ifu_axi_arvalid;
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wire ifu_axi_arready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid;
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wire [ 31:0] ifu_axi_araddr;
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wire [ 3:0] ifu_axi_arregion;
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wire [ 7:0] ifu_axi_arlen;
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wire [ 2:0] ifu_axi_arsize;
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wire [ 1:0] ifu_axi_arburst;
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wire ifu_axi_arlock;
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wire [ 3:0] ifu_axi_arcache;
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wire [ 2:0] ifu_axi_arprot;
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wire [ 3:0] ifu_axi_arqos;
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wire ifu_axi_rvalid;
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wire ifu_axi_rready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid;
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wire [ 63:0] ifu_axi_rdata;
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wire [ 1:0] ifu_axi_rresp;
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wire ifu_axi_rlast;
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//-------------------------- SB AXI signals--------------------------
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// AXI Write Channels
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wire sb_axi_awvalid;
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wire sb_axi_awready;
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wire [ `RV_SB_BUS_TAG-1:0] sb_axi_awid;
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wire [ 31:0] sb_axi_awaddr;
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wire [ 3:0] sb_axi_awregion;
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wire [ 7:0] sb_axi_awlen;
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wire [ 2:0] sb_axi_awsize;
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wire [ 1:0] sb_axi_awburst;
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wire sb_axi_awlock;
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wire [ 3:0] sb_axi_awcache;
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wire [ 2:0] sb_axi_awprot;
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wire [ 3:0] sb_axi_awqos;
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wire sb_axi_wvalid;
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wire sb_axi_wready;
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wire [ 63:0] sb_axi_wdata;
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wire [ 7:0] sb_axi_wstrb;
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wire sb_axi_wlast;
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wire sb_axi_bvalid;
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wire sb_axi_bready;
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wire [ 1:0] sb_axi_bresp;
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wire [ `RV_SB_BUS_TAG-1:0] sb_axi_bid;
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// AXI Read Channels
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wire sb_axi_arvalid;
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wire sb_axi_arready;
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wire [ `RV_SB_BUS_TAG-1:0] sb_axi_arid;
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wire [ 31:0] sb_axi_araddr;
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wire [ 3:0] sb_axi_arregion;
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wire [ 7:0] sb_axi_arlen;
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wire [ 2:0] sb_axi_arsize;
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wire [ 1:0] sb_axi_arburst;
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wire sb_axi_arlock;
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wire [ 3:0] sb_axi_arcache;
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wire [ 2:0] sb_axi_arprot;
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wire [ 3:0] sb_axi_arqos;
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wire sb_axi_rvalid;
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wire sb_axi_rready;
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wire [ `RV_SB_BUS_TAG-1:0] sb_axi_rid;
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wire [ 63:0] sb_axi_rdata;
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wire [ 1:0] sb_axi_rresp;
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wire sb_axi_rlast;
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//-------------------------- DMA AXI signals--------------------------
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// AXI Write Channels
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wire dma_axi_awvalid;
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wire dma_axi_awready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_awid;
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wire [ 31:0] dma_axi_awaddr;
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wire [ 2:0] dma_axi_awsize;
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wire [ 2:0] dma_axi_awprot;
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wire [ 7:0] dma_axi_awlen;
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wire [ 1:0] dma_axi_awburst;
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wire dma_axi_wvalid;
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wire dma_axi_wready;
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wire [ 63:0] dma_axi_wdata;
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wire [ 7:0] dma_axi_wstrb;
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wire dma_axi_wlast;
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wire dma_axi_bvalid;
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wire dma_axi_bready;
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wire [ 1:0] dma_axi_bresp;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_bid;
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// AXI Read Channels
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wire dma_axi_arvalid;
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wire dma_axi_arready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_arid;
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wire [ 31:0] dma_axi_araddr;
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wire [ 2:0] dma_axi_arsize;
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wire [ 2:0] dma_axi_arprot;
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wire [ 7:0] dma_axi_arlen;
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wire [ 1:0] dma_axi_arburst;
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wire dma_axi_rvalid;
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wire dma_axi_rready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_rid;
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wire [ 63:0] dma_axi_rdata;
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wire [ 1:0] dma_axi_rresp;
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wire dma_axi_rlast;
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wire lmem_axi_arvalid;
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wire lmem_axi_arready;
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wire lmem_axi_rvalid;
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wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_rid;
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wire [ 1:0] lmem_axi_rresp;
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wire [ 63:0] lmem_axi_rdata;
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wire lmem_axi_rlast;
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wire lmem_axi_rready;
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wire lmem_axi_awvalid;
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wire lmem_axi_awready;
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wire lmem_axi_wvalid;
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wire lmem_axi_wready;
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wire [ 1:0] lmem_axi_bresp;
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wire lmem_axi_bvalid;
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wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_bid;
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wire lmem_axi_bready;
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initial begin
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jtag_id[31:28] = 4'b1;
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jtag_id[27:12] = '0;
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jtag_id[11:1] = 11'h45;
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reset_vector = 32'h80000000;
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nmi_vector = 32'hee000000;
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nmi_int = 0;
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$readmemh("program.hex", lmem.mem);
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$readmemh("program.hex", imem.mem);
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end
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swerv_wrapper rvtop (
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.rst_l (rst),
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.dbg_rst_l(dbg_rst),
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.clk (clk),
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.rst_vec (reset_vector[31:1]),
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.nmi_int (nmi_int),
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.nmi_vec (nmi_vector[31:1]),
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.jtag_id (jtag_id[31:1]),
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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.lsu_axi_awvalid (lsu_axi_awvalid),
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.lsu_axi_awready (lsu_axi_awready),
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.lsu_axi_awid (lsu_axi_awid),
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.lsu_axi_awaddr (lsu_axi_awaddr),
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.lsu_axi_awregion(lsu_axi_awregion),
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.lsu_axi_awlen (lsu_axi_awlen),
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.lsu_axi_awsize (lsu_axi_awsize),
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.lsu_axi_awburst (lsu_axi_awburst),
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.lsu_axi_awlock (lsu_axi_awlock),
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.lsu_axi_awcache (lsu_axi_awcache),
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.lsu_axi_awprot (lsu_axi_awprot),
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.lsu_axi_awqos (lsu_axi_awqos),
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.lsu_axi_wvalid(lsu_axi_wvalid),
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.lsu_axi_wready(lsu_axi_wready),
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.lsu_axi_wdata (lsu_axi_wdata),
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.lsu_axi_wstrb (lsu_axi_wstrb),
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.lsu_axi_wlast (lsu_axi_wlast),
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.lsu_axi_bvalid(lsu_axi_bvalid),
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.lsu_axi_bready(lsu_axi_bready),
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.lsu_axi_bresp (lsu_axi_bresp),
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.lsu_axi_bid (lsu_axi_bid),
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.lsu_axi_arvalid (lsu_axi_arvalid),
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.lsu_axi_arready (lsu_axi_arready),
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.lsu_axi_arid (lsu_axi_arid),
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.lsu_axi_araddr (lsu_axi_araddr),
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.lsu_axi_arregion(lsu_axi_arregion),
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.lsu_axi_arlen (lsu_axi_arlen),
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.lsu_axi_arsize (lsu_axi_arsize),
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.lsu_axi_arburst (lsu_axi_arburst),
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.lsu_axi_arlock (lsu_axi_arlock),
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.lsu_axi_arcache (lsu_axi_arcache),
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.lsu_axi_arprot (lsu_axi_arprot),
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.lsu_axi_arqos (lsu_axi_arqos),
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.lsu_axi_rvalid(lsu_axi_rvalid),
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.lsu_axi_rready(lsu_axi_rready),
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.lsu_axi_rid (lsu_axi_rid),
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.lsu_axi_rdata (lsu_axi_rdata),
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.lsu_axi_rresp (lsu_axi_rresp),
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.lsu_axi_rlast (lsu_axi_rlast),
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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.ifu_axi_awvalid (ifu_axi_awvalid),
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.ifu_axi_awready (ifu_axi_awready),
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.ifu_axi_awid (ifu_axi_awid),
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.ifu_axi_awaddr (ifu_axi_awaddr),
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.ifu_axi_awregion(ifu_axi_awregion),
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.ifu_axi_awlen (ifu_axi_awlen),
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.ifu_axi_awsize (ifu_axi_awsize),
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.ifu_axi_awburst (ifu_axi_awburst),
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.ifu_axi_awlock (ifu_axi_awlock),
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.ifu_axi_awcache (ifu_axi_awcache),
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.ifu_axi_awprot (ifu_axi_awprot),
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.ifu_axi_awqos (ifu_axi_awqos),
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.ifu_axi_wvalid(ifu_axi_wvalid),
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.ifu_axi_wready(ifu_axi_wready),
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.ifu_axi_wdata (ifu_axi_wdata),
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.ifu_axi_wstrb (ifu_axi_wstrb),
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.ifu_axi_wlast (ifu_axi_wlast),
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.ifu_axi_bvalid(ifu_axi_bvalid),
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.ifu_axi_bready(ifu_axi_bready),
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.ifu_axi_bresp (ifu_axi_bresp),
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.ifu_axi_bid (ifu_axi_bid),
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.ifu_axi_arvalid (ifu_axi_arvalid),
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.ifu_axi_arready (ifu_axi_arready),
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.ifu_axi_arid (ifu_axi_arid),
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.ifu_axi_araddr (ifu_axi_araddr),
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.ifu_axi_arregion(ifu_axi_arregion),
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.ifu_axi_arlen (ifu_axi_arlen),
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.ifu_axi_arsize (ifu_axi_arsize),
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.ifu_axi_arburst (ifu_axi_arburst),
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.ifu_axi_arlock (ifu_axi_arlock),
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.ifu_axi_arcache (ifu_axi_arcache),
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.ifu_axi_arprot (ifu_axi_arprot),
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.ifu_axi_arqos (ifu_axi_arqos),
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.ifu_axi_rvalid(ifu_axi_rvalid),
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.ifu_axi_rready(ifu_axi_rready),
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.ifu_axi_rid (ifu_axi_rid),
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.ifu_axi_rdata (ifu_axi_rdata),
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.ifu_axi_rresp (ifu_axi_rresp),
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.ifu_axi_rlast (ifu_axi_rlast),
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//-------------------------- SB AXI signals--------------------------
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// AXI Write Channels
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.sb_axi_awvalid (sb_axi_awvalid),
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.sb_axi_awready (sb_axi_awready),
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.sb_axi_awid (sb_axi_awid),
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.sb_axi_awaddr (sb_axi_awaddr),
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.sb_axi_awregion(sb_axi_awregion),
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.sb_axi_awlen (sb_axi_awlen),
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.sb_axi_awsize (sb_axi_awsize),
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.sb_axi_awburst (sb_axi_awburst),
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.sb_axi_awlock (sb_axi_awlock),
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.sb_axi_awcache (sb_axi_awcache),
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.sb_axi_awprot (sb_axi_awprot),
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.sb_axi_awqos (sb_axi_awqos),
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.sb_axi_wvalid(sb_axi_wvalid),
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.sb_axi_wready(sb_axi_wready),
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.sb_axi_wdata (sb_axi_wdata),
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.sb_axi_wstrb (sb_axi_wstrb),
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.sb_axi_wlast (sb_axi_wlast),
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.sb_axi_bvalid(sb_axi_bvalid),
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.sb_axi_bready(sb_axi_bready),
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.sb_axi_bresp (sb_axi_bresp),
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.sb_axi_bid (sb_axi_bid),
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.sb_axi_arvalid (sb_axi_arvalid),
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.sb_axi_arready (sb_axi_arready),
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.sb_axi_arid (sb_axi_arid),
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.sb_axi_araddr (sb_axi_araddr),
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.sb_axi_arregion(sb_axi_arregion),
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.sb_axi_arlen (sb_axi_arlen),
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.sb_axi_arsize (sb_axi_arsize),
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.sb_axi_arburst (sb_axi_arburst),
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.sb_axi_arlock (sb_axi_arlock),
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.sb_axi_arcache (sb_axi_arcache),
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.sb_axi_arprot (sb_axi_arprot),
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.sb_axi_arqos (sb_axi_arqos),
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.sb_axi_rvalid(sb_axi_rvalid),
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.sb_axi_rready(sb_axi_rready),
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.sb_axi_rid (sb_axi_rid),
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.sb_axi_rdata (sb_axi_rdata),
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.sb_axi_rresp (sb_axi_rresp),
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.sb_axi_rlast (sb_axi_rlast),
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//-------------------------- DMA AXI signals--------------------------
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// AXI Write Channels
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.dma_axi_awvalid(dma_axi_awvalid),
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.dma_axi_awready(dma_axi_awready),
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.dma_axi_awid ('0), // ids are not used on DMA since it always responses in order
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.dma_axi_awaddr(lsu_axi_awaddr),
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.dma_axi_awsize(lsu_axi_awsize),
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.dma_axi_awprot('0),
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.dma_axi_awlen('0),
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.dma_axi_awburst('0),
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.dma_axi_wvalid(dma_axi_wvalid),
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.dma_axi_wready(dma_axi_wready),
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.dma_axi_wdata (lsu_axi_wdata),
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.dma_axi_wstrb (lsu_axi_wstrb),
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.dma_axi_wlast (1'b1),
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.dma_axi_bvalid(dma_axi_bvalid),
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.dma_axi_bready(dma_axi_bready),
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.dma_axi_bresp (dma_axi_bresp),
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.dma_axi_bid (),
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.dma_axi_arvalid(dma_axi_arvalid),
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.dma_axi_arready(dma_axi_arready),
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.dma_axi_arid ('0),
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.dma_axi_araddr (lsu_axi_araddr),
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.dma_axi_arsize (lsu_axi_arsize),
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.dma_axi_arprot ('0),
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.dma_axi_arlen ('0),
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.dma_axi_arburst('0),
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.dma_axi_rvalid(dma_axi_rvalid),
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.dma_axi_rready(dma_axi_rready),
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.dma_axi_rid (),
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.dma_axi_rdata (dma_axi_rdata),
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.dma_axi_rresp (dma_axi_rresp),
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.dma_axi_rlast (dma_axi_rlast),
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.timer_int (1'b0),
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.extintsrc_req('0),
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.lsu_bus_clk_en(1'b1),
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.ifu_bus_clk_en(1'b1),
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.dbg_bus_clk_en(1'b1),
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.dma_bus_clk_en(1'b1),
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.trace_rv_i_insn_ip (trace_rv_i_insn_ip),
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.trace_rv_i_address_ip (trace_rv_i_address_ip),
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.trace_rv_i_valid_ip (trace_rv_i_valid_ip),
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.trace_rv_i_exception_ip(trace_rv_i_exception_ip),
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.trace_rv_i_ecause_ip (trace_rv_i_ecause_ip),
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.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
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.trace_rv_i_tval_ip (trace_rv_i_tval_ip),
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.jtag_tck (jtag_tck),
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.jtag_tms (jtag_tms),
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.jtag_tdi (jtag_tdi),
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.jtag_trst_n(jtag_trst_n),
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.jtag_tdo (jtag_tdo),
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.mpc_debug_halt_ack(mpc_debug_halt_ack),
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.mpc_debug_halt_req(1'b0),
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.mpc_debug_run_ack (mpc_debug_run_ack),
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.mpc_debug_run_req (1'b1),
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.mpc_reset_run_req (1'b1),
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.debug_brkpt_status(debug_brkpt_status),
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|
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.i_cpu_halt_req (1'b0),
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.o_cpu_halt_ack (o_cpu_halt_ack),
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.o_cpu_halt_status (o_cpu_halt_status),
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.i_cpu_run_req (1'b0),
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.o_debug_mode_status(o_debug_mode_status),
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.o_cpu_run_ack (o_cpu_run_ack),
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.dec_tlu_perfcnt0(dec_tlu_perfcnt0),
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.dec_tlu_perfcnt1(dec_tlu_perfcnt1),
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.dec_tlu_perfcnt2(dec_tlu_perfcnt2),
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.dec_tlu_perfcnt3(dec_tlu_perfcnt3),
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.scan_mode (1'b0),
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.mbist_mode(1'b0)
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);
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axi_slv #(
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.TAGW(`RV_IFU_BUS_TAG)
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) imem (
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.aclk(clk),
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.rst_l(rst),
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.arvalid(ifu_axi_arvalid),
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.arready(ifu_axi_arready),
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.araddr(ifu_axi_araddr),
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.arid(ifu_axi_arid),
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.arlen(ifu_axi_arlen),
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.arburst(ifu_axi_arburst),
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.arsize(ifu_axi_arsize),
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.rvalid(ifu_axi_rvalid),
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.rready(ifu_axi_rready),
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.rdata(ifu_axi_rdata),
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.rresp(ifu_axi_rresp),
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.rid(ifu_axi_rid),
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.rlast(ifu_axi_rlast),
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.awvalid(1'b0),
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.awready(),
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.awaddr('0),
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.awid('0),
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.awlen('0),
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.awburst('0),
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.awsize('0),
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.wdata ('0),
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.wstrb ('0),
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.wvalid(1'b0),
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.wready(),
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.bvalid(),
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.bready(1'b0),
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.bresp(),
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.bid()
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|
);
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defparam lmem.TAGW = `RV_LSU_BUS_TAG;
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//axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem(
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axi_slv lmem (
|
|
.aclk(clk),
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|
.rst_l(rst),
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|
.arvalid(lmem_axi_arvalid),
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|
.arready(lmem_axi_arready),
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|
.araddr(lsu_axi_araddr),
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|
.arid(lsu_axi_arid),
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|
.arlen(lsu_axi_arlen),
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.arburst(lsu_axi_arburst),
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|
.arsize(lsu_axi_arsize),
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|
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|
.rvalid(lmem_axi_rvalid),
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|
.rready(lmem_axi_rready),
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|
.rdata(lmem_axi_rdata),
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|
.rresp(lmem_axi_rresp),
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|
.rid(lmem_axi_rid),
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|
.rlast(lmem_axi_rlast),
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|
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|
.awvalid(lmem_axi_awvalid),
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|
.awready(lmem_axi_awready),
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.awaddr(lsu_axi_awaddr),
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|
.awid(lsu_axi_awid),
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|
.awlen(lsu_axi_awlen),
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|
.awburst(lsu_axi_awburst),
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|
.awsize(lsu_axi_awsize),
|
|
|
|
.wdata (lsu_axi_wdata),
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|
.wstrb (lsu_axi_wstrb),
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|
.wvalid(lmem_axi_wvalid),
|
|
.wready(lmem_axi_wready),
|
|
|
|
.bvalid(lmem_axi_bvalid),
|
|
.bready(lmem_axi_bready),
|
|
.bresp(lmem_axi_bresp),
|
|
.bid(lmem_axi_bid)
|
|
);
|
|
|
|
axi_lsu_dma_bridge #(`RV_LSU_BUS_TAG, `RV_LSU_BUS_TAG) bridge (
|
|
.clk(clk),
|
|
.reset_l(rst),
|
|
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|
.m_arvalid(lsu_axi_arvalid),
|
|
.m_arid(lsu_axi_arid),
|
|
.m_araddr(lsu_axi_araddr),
|
|
.m_arready(lsu_axi_arready),
|
|
|
|
.m_rvalid(lsu_axi_rvalid),
|
|
.m_rready(lsu_axi_rready),
|
|
.m_rdata(lsu_axi_rdata),
|
|
.m_rid(lsu_axi_rid),
|
|
.m_rresp(lsu_axi_rresp),
|
|
.m_rlast(lsu_axi_rlast),
|
|
|
|
.m_awvalid(lsu_axi_awvalid),
|
|
.m_awid(lsu_axi_awid),
|
|
.m_awaddr(lsu_axi_awaddr),
|
|
.m_awready(lsu_axi_awready),
|
|
|
|
.m_wvalid(lsu_axi_wvalid),
|
|
.m_wready(lsu_axi_wready),
|
|
|
|
.m_bresp(lsu_axi_bresp),
|
|
.m_bvalid(lsu_axi_bvalid),
|
|
.m_bid(lsu_axi_bid),
|
|
.m_bready(lsu_axi_bready),
|
|
|
|
.s0_arvalid(lmem_axi_arvalid),
|
|
.s0_arready(lmem_axi_arready),
|
|
|
|
.s0_rvalid(lmem_axi_rvalid),
|
|
.s0_rid(lmem_axi_rid),
|
|
.s0_rresp(lmem_axi_rresp),
|
|
.s0_rdata(lmem_axi_rdata),
|
|
.s0_rlast(lmem_axi_rlast),
|
|
.s0_rready(lmem_axi_rready),
|
|
|
|
.s0_awvalid(lmem_axi_awvalid),
|
|
.s0_awready(lmem_axi_awready),
|
|
|
|
.s0_wvalid(lmem_axi_wvalid),
|
|
.s0_wready(lmem_axi_wready),
|
|
.s0_bresp(lmem_axi_bresp),
|
|
.s0_bvalid(lmem_axi_bvalid),
|
|
.s0_bid(lmem_axi_bid),
|
|
.s0_bready(lmem_axi_bready),
|
|
|
|
|
|
.s1_arvalid(dma_axi_arvalid),
|
|
.s1_arready(dma_axi_arready),
|
|
|
|
.s1_rvalid(dma_axi_rvalid),
|
|
.s1_rresp (dma_axi_rresp),
|
|
.s1_rdata (dma_axi_rdata),
|
|
.s1_rlast (dma_axi_rlast),
|
|
.s1_rready(dma_axi_rready),
|
|
|
|
.s1_awvalid(dma_axi_awvalid),
|
|
.s1_awready(dma_axi_awready),
|
|
|
|
.s1_wvalid(dma_axi_wvalid),
|
|
.s1_wready(dma_axi_wready),
|
|
|
|
.s1_bresp (dma_axi_bresp),
|
|
.s1_bvalid(dma_axi_bvalid),
|
|
.s1_bready(dma_axi_bready)
|
|
|
|
);
|
|
|
|
|
|
endmodule
|