61 lines
1.5 KiB
Bash
Executable File
61 lines
1.5 KiB
Bash
Executable File
#!/bin/bash
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set -ex
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PWD=$(pwd)
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SOC=$PWD/../soc/
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SOCFILE=../soc/soc_top.mk
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DEFINE_DIR=$PWD/build
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DEFINE="${DEFINE_DIR}/el2_pdef.vh ${DEFINE_DIR}/common_defines.vh"
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mkdir -p gen
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rm -rf gen/*
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mkdir gen/design
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YOSYS_COARSE=true
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YOSYS_GLOBRST=false
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YOSYS_SPLITNETS=false
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TOP="soc_top"
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RTL_FILES="$DEFINE $(cat $SOCFILE | sed 's/[[:space:]]//g' | sed '/^$/d' | sed -e "s!^!$SOC!" | tr '\n' ' ')"
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sv2v -I${DEFINE_DIR} $RTL_FILES > gen/soc_top.v
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{
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echo "read_verilog gen/soc_top.v"
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if test -n "$TOP"; then
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echo "hierarchy -check -top $TOP"
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else
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echo "hierarchy -check"
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fi
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if $YOSYS_GLOBRST; then
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# insertation of global reset (e.g. for FPGA cores)
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echo "add -global_input globrst 1"
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echo "proc -global_arst globrst"
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fi
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echo "synth -run coarse; opt -fine"
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# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
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if ! $YOSYS_COARSE; then
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echo "memory_map; techmap; opt; abc -dff; clean"
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fi
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if $YOSYS_SPLITNETS; then
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# icarus verilog has a performance problems when there are
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# dependencies between the bits of a long vector
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echo "splitnets; clean"
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fi
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if $YOSYS_COARSE; then
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echo "write_verilog -noexpr -noattr gen/synth.v"
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else
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echo "select -assert-none t:\$[!_]"
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echo "write_verilog -noattr gen/synth.v"
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fi
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echo "synth_ecp5 -top $TOP -json gen/soc.json"
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# echo "synth_xilinx -top $TOP"
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} > gen/synth.ys
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yosys -v2 -l gen/synth.log gen/synth.ys
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nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1 --json gen/soc.json
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