472 lines
17 KiB
Systemverilog
472 lines
17 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Function: Top wrapper file with el2_swerv/mem instantiated inside
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// Comments:
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//
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//********************************************************************************
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module el2_swerv_wrapper
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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) (
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input logic clk,
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input logic rst_l,
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input logic dbg_rst_l,
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input logic [31:1] rst_vec,
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input logic nmi_int,
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input logic [31:1] nmi_vec,
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input logic [31:1] jtag_id,
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output logic [31:0] trace_rv_i_insn_ip,
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output logic [31:0] trace_rv_i_address_ip,
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output logic trace_rv_i_valid_ip,
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output logic trace_rv_i_exception_ip,
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output logic [ 4:0] trace_rv_i_ecause_ip,
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output logic trace_rv_i_interrupt_ip,
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output logic [31:0] trace_rv_i_tval_ip,
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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output logic lsu_axi_awvalid,
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input logic lsu_axi_awready,
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output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
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output logic [ 31:0] lsu_axi_awaddr,
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output logic [ 3:0] lsu_axi_awregion,
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output logic [ 7:0] lsu_axi_awlen,
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output logic [ 2:0] lsu_axi_awsize,
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output logic [ 1:0] lsu_axi_awburst,
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output logic lsu_axi_awlock,
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output logic [ 3:0] lsu_axi_awcache,
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output logic [ 2:0] lsu_axi_awprot,
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output logic [ 3:0] lsu_axi_awqos,
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output logic lsu_axi_wvalid,
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input logic lsu_axi_wready,
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output logic [63:0] lsu_axi_wdata,
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output logic [ 7:0] lsu_axi_wstrb,
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output logic lsu_axi_wlast,
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input logic lsu_axi_bvalid,
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output logic lsu_axi_bready,
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input logic [ 1:0] lsu_axi_bresp,
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input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
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// AXI Read Channels
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output logic lsu_axi_arvalid,
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input logic lsu_axi_arready,
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output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
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output logic [ 31:0] lsu_axi_araddr,
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output logic [ 3:0] lsu_axi_arregion,
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output logic [ 7:0] lsu_axi_arlen,
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output logic [ 2:0] lsu_axi_arsize,
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output logic [ 1:0] lsu_axi_arburst,
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output logic lsu_axi_arlock,
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output logic [ 3:0] lsu_axi_arcache,
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output logic [ 2:0] lsu_axi_arprot,
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output logic [ 3:0] lsu_axi_arqos,
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input logic lsu_axi_rvalid,
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output logic lsu_axi_rready,
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input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
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input logic [ 63:0] lsu_axi_rdata,
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input logic [ 1:0] lsu_axi_rresp,
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input logic lsu_axi_rlast,
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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output logic ifu_axi_awvalid,
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input logic ifu_axi_awready,
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output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
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output logic [ 31:0] ifu_axi_awaddr,
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output logic [ 3:0] ifu_axi_awregion,
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output logic [ 7:0] ifu_axi_awlen,
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output logic [ 2:0] ifu_axi_awsize,
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output logic [ 1:0] ifu_axi_awburst,
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output logic ifu_axi_awlock,
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output logic [ 3:0] ifu_axi_awcache,
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output logic [ 2:0] ifu_axi_awprot,
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output logic [ 3:0] ifu_axi_awqos,
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output logic ifu_axi_wvalid,
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input logic ifu_axi_wready,
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output logic [63:0] ifu_axi_wdata,
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output logic [ 7:0] ifu_axi_wstrb,
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output logic ifu_axi_wlast,
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input logic ifu_axi_bvalid,
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output logic ifu_axi_bready,
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input logic [ 1:0] ifu_axi_bresp,
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input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
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// AXI Read Channels
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output logic ifu_axi_arvalid,
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input logic ifu_axi_arready,
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output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
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output logic [ 31:0] ifu_axi_araddr,
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output logic [ 3:0] ifu_axi_arregion,
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output logic [ 7:0] ifu_axi_arlen,
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output logic [ 2:0] ifu_axi_arsize,
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output logic [ 1:0] ifu_axi_arburst,
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output logic ifu_axi_arlock,
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output logic [ 3:0] ifu_axi_arcache,
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output logic [ 2:0] ifu_axi_arprot,
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output logic [ 3:0] ifu_axi_arqos,
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input logic ifu_axi_rvalid,
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output logic ifu_axi_rready,
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input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
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input logic [ 63:0] ifu_axi_rdata,
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input logic [ 1:0] ifu_axi_rresp,
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input logic ifu_axi_rlast,
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//-------------------------- SB AXI signals--------------------------
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// AXI Write Channels
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output logic sb_axi_awvalid,
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input logic sb_axi_awready,
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output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
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output logic [ 31:0] sb_axi_awaddr,
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output logic [ 3:0] sb_axi_awregion,
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output logic [ 7:0] sb_axi_awlen,
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output logic [ 2:0] sb_axi_awsize,
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output logic [ 1:0] sb_axi_awburst,
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output logic sb_axi_awlock,
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output logic [ 3:0] sb_axi_awcache,
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output logic [ 2:0] sb_axi_awprot,
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output logic [ 3:0] sb_axi_awqos,
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output logic sb_axi_wvalid,
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input logic sb_axi_wready,
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output logic [63:0] sb_axi_wdata,
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output logic [ 7:0] sb_axi_wstrb,
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output logic sb_axi_wlast,
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input logic sb_axi_bvalid,
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output logic sb_axi_bready,
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input logic [ 1:0] sb_axi_bresp,
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input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
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// AXI Read Channels
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output logic sb_axi_arvalid,
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input logic sb_axi_arready,
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output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
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output logic [ 31:0] sb_axi_araddr,
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output logic [ 3:0] sb_axi_arregion,
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output logic [ 7:0] sb_axi_arlen,
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output logic [ 2:0] sb_axi_arsize,
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output logic [ 1:0] sb_axi_arburst,
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output logic sb_axi_arlock,
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output logic [ 3:0] sb_axi_arcache,
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output logic [ 2:0] sb_axi_arprot,
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output logic [ 3:0] sb_axi_arqos,
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input logic sb_axi_rvalid,
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output logic sb_axi_rready,
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input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
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input logic [ 63:0] sb_axi_rdata,
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input logic [ 1:0] sb_axi_rresp,
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input logic sb_axi_rlast,
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//-------------------------- DMA AXI signals--------------------------
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// AXI Write Channels
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input logic dma_axi_awvalid,
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output logic dma_axi_awready,
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input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
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input logic [ 31:0] dma_axi_awaddr,
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input logic [ 2:0] dma_axi_awsize,
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input logic [ 2:0] dma_axi_awprot,
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input logic [ 7:0] dma_axi_awlen,
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input logic [ 1:0] dma_axi_awburst,
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input logic dma_axi_wvalid,
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output logic dma_axi_wready,
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input logic [63:0] dma_axi_wdata,
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input logic [ 7:0] dma_axi_wstrb,
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input logic dma_axi_wlast,
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output logic dma_axi_bvalid,
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input logic dma_axi_bready,
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output logic [ 1:0] dma_axi_bresp,
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output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
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// AXI Read Channels
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input logic dma_axi_arvalid,
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output logic dma_axi_arready,
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input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
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input logic [ 31:0] dma_axi_araddr,
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input logic [ 2:0] dma_axi_arsize,
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input logic [ 2:0] dma_axi_arprot,
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input logic [ 7:0] dma_axi_arlen,
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input logic [ 1:0] dma_axi_arburst,
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output logic dma_axi_rvalid,
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input logic dma_axi_rready,
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output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
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output logic [ 63:0] dma_axi_rdata,
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output logic [ 1:0] dma_axi_rresp,
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output logic dma_axi_rlast,
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// clk ratio signals
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input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
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input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
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input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
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input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
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// all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
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input el2_dccm_ext_in_pkt_t [pt.DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
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input el2_ccm_ext_in_pkt_t [pt.ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt,
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input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
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input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
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input logic timer_int,
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input logic soft_int,
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input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
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output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
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output logic dec_tlu_perfcnt1,
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output logic dec_tlu_perfcnt2,
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output logic dec_tlu_perfcnt3,
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// ports added by the soc team
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input logic jtag_tck, // JTAG clk
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input logic jtag_tms, // JTAG TMS
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input logic jtag_tdi, // JTAG tdi
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input logic jtag_trst_n, // JTAG Reset
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output logic jtag_tdo, // JTAG TDO
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input logic [31:4] core_id,
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// external MPC halt/run interface
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input logic mpc_debug_halt_req, // Async halt request
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input logic mpc_debug_run_req, // Async run request
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input logic mpc_reset_run_req, // Run/halt after reset
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output logic mpc_debug_halt_ack, // Halt ack
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output logic mpc_debug_run_ack, // Run ack
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output logic debug_brkpt_status, // debug breakpoint
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input logic i_cpu_halt_req, // Async halt req to CPU
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output logic o_cpu_halt_ack, // core response to halt
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output logic o_cpu_halt_status, // 1'b1 indicates core is halted
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output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
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input logic i_cpu_run_req, // Async restart req to CPU
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output logic o_cpu_run_ack, // Core response to run req
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input logic scan_mode, // To enable scan mode
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input logic mbist_mode // to enable mbist
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);
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logic active_l2clk;
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logic free_l2clk;
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// DCCM ports
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logic dccm_wren;
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logic dccm_rden;
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logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;
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logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;
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logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;
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logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;
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logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;
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logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;
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logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
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logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
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// PIC ports
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// Icache & Itag ports
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logic [31:1] ic_rw_addr;
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logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en; // Which way to write
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logic ic_rd_en;
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logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).
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logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit; // ic_rd_hit[3:0]
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logic ic_tag_perr; // Ic tag parity error
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logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr; // Read/Write addresss to the Icache.
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logic ic_debug_rd_en; // Icache debug rd
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logic ic_debug_wr_en; // Icache debug wr
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logic ic_debug_tag_array; // Debug tag array
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logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way; // Debug way. Rd or Wr.
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logic [25:0] ictag_debug_rd_data; // Debug icache tag.
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logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
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logic [63:0] ic_rd_data;
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logic [70:0] ic_debug_rd_data; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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logic [70:0] ic_debug_wr_data; // Debug wr cache.
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logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr; // ecc error per bank
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logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr; // parity error per bank
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logic [63:0] ic_premux_data;
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logic ic_sel_premux_data;
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// ICCM ports
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logic [pt.ICCM_BITS-1:1] iccm_rw_addr;
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logic iccm_wren;
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logic iccm_rden;
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logic [2:0] iccm_wr_size;
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logic [77:0] iccm_wr_data;
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logic iccm_buf_correct_ecc;
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logic iccm_correction_state;
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logic [63:0] iccm_rd_data;
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logic [77:0] iccm_rd_data_ecc;
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logic core_rst_l; // Core reset including rst_l and dbg_rst_l
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logic jtag_tdoEn;
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logic dccm_clk_override;
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logic icm_clk_override;
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logic dec_tlu_core_ecc_disable;
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// zero out the signals not presented at the wrapper instantiation level
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//// AHB LITE BUS
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logic [31:0] haddr;
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logic [ 2:0] hburst;
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logic hmastlock;
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logic [ 3:0] hprot;
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logic [ 2:0] hsize;
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logic [ 1:0] htrans;
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logic hwrite;
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logic [63:0] hrdata;
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logic hready;
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logic hresp;
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// LSU AHB Master
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logic [31:0] lsu_haddr;
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logic [ 2:0] lsu_hburst;
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logic lsu_hmastlock;
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logic [ 3:0] lsu_hprot;
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logic [ 2:0] lsu_hsize;
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logic [ 1:0] lsu_htrans;
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logic lsu_hwrite;
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logic [63:0] lsu_hwdata;
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logic [63:0] lsu_hrdata;
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logic lsu_hready;
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logic lsu_hresp;
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// Debug Syster Bus AHB
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logic [31:0] sb_haddr;
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logic [ 2:0] sb_hburst;
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logic sb_hmastlock;
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logic [ 3:0] sb_hprot;
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logic [ 2:0] sb_hsize;
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logic [ 1:0] sb_htrans;
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logic sb_hwrite;
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logic [63:0] sb_hwdata;
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logic [63:0] sb_hrdata;
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logic sb_hready;
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logic sb_hresp;
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// DMA Slave
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logic dma_hsel;
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logic [31:0] dma_haddr;
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logic [ 2:0] dma_hburst;
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logic dma_hmastlock;
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logic [ 3:0] dma_hprot;
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logic [ 2:0] dma_hsize;
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logic [ 1:0] dma_htrans;
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logic dma_hwrite;
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logic [63:0] dma_hwdata;
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logic dma_hreadyin;
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logic [63:0] dma_hrdata;
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logic dma_hreadyout;
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logic dma_hresp;
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// AHB
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assign hrdata[63:0] = '0;
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assign hready = '0;
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assign hresp = '0;
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// LSU
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assign lsu_hrdata[63:0] = '0;
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assign lsu_hready = '0;
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assign lsu_hresp = '0;
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// Debu
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assign sb_hrdata[63:0] = '0;
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assign sb_hready = '0;
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assign sb_hresp = '0;
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// DMA
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assign dma_hsel = '0;
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assign dma_haddr[31:0] = '0;
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assign dma_hburst[2:0] = '0;
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assign dma_hmastlock = '0;
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assign dma_hprot[3:0] = '0;
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assign dma_hsize[2:0] = '0;
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assign dma_htrans[1:0] = '0;
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assign dma_hwrite = '0;
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assign dma_hwdata[63:0] = '0;
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assign dma_hreadyin = '0;
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|
|
|
logic dmi_reg_en;
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|
logic [ 6:0] dmi_reg_addr;
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|
logic dmi_reg_wr_en;
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|
logic [31:0] dmi_reg_wdata;
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|
logic [31:0] dmi_reg_rdata;
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|
|
|
// Instantiate the el2_swerv core
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|
el2_swerv #(
|
|
.pt(pt)
|
|
) swerv (
|
|
.clk(clk),
|
|
.*
|
|
);
|
|
|
|
// Instantiate the mem
|
|
el2_mem #(
|
|
.pt(pt)
|
|
) mem (
|
|
.clk (active_l2clk),
|
|
.rst_l(core_rst_l),
|
|
.*
|
|
);
|
|
|
|
|
|
// JTAG/DMI instance
|
|
dmi_wrapper dmi_wrapper (
|
|
// JTAG signals
|
|
.trst_n (jtag_trst_n), // JTAG reset
|
|
.tck (jtag_tck), // JTAG clock
|
|
.tms (jtag_tms), // Test mode select
|
|
.tdi (jtag_tdi), // Test Data Input
|
|
.tdo (jtag_tdo), // Test Data Output
|
|
.tdoEnable (),
|
|
// Processor Signals
|
|
.core_rst_n (dbg_rst_l), // Debug reset, active low
|
|
.core_clk (clk), // Core clock
|
|
.jtag_id (jtag_id), // JTAG ID
|
|
.rd_data (dmi_reg_rdata), // Read data from Processor
|
|
.reg_wr_data (dmi_reg_wdata), // Write data to Processor
|
|
.reg_wr_addr (dmi_reg_addr), // Write address to Processor
|
|
.reg_en (dmi_reg_en), // Write interface bit to Processor
|
|
.reg_wr_en (dmi_reg_wr_en), // Write enable to Processor
|
|
.dmi_hard_reset()
|
|
);
|
|
|
|
endmodule
|